Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 29
PIC18FXX8
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO V
DD
)
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO V
DD
)
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
T
PWRT
T
OST
T
PWRT
T
OST
V
DD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
T
PLL
Note:
T
OST
= 1024 clock cycles.
T
PLL
≈ 2 ms max. First three stages of the PWRT timer.