Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 357
PIC18FXX8
FIGURE 27-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-22:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 27-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 27-5 for load conditions.
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
120
TckH2dtV SYNC XMIT (Master & Slave)
Clock High to Data-Out Valid
PIC18FXX8
—
50
ns
PIC18LFXX8
—
150
ns
121
Tckrf
Clock Out Rise Time and Fall Time
(Master mode)
(Master mode)
PIC18FXX8
—
25
ns
PIC18LFXX8
—
60
ns
122
Tdtrf
Data-Out Rise Time and Fall Time
PIC18FXX8
—
25
ns
PIC18LFXX8
—
60
ns
Note: Refer to Figure 27-5 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
125
TdtV2ckl
SYNC RCV (Master & Slave)
Data-Hold before CK
Data-Hold before CK
↓ (DT hold time)
10
—
ns
126
TckL2dtl
Data-Hold after CK
↓ (DT hold time)
15
—
ns