Microchip Technology DM164134 Data Sheet

DS41159E-page 96

© 2006 Microchip Technology Inc.

PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB. 

Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2 register).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.

Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit RBIF (INTCON register). 

This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:

a)

Any read or write of PORTB (except with the
MOVFF

 instruction). This will end the mismatch

condition.

b)

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.

CLRF

PORTB

; Initialize PORTB by

; clearing output 

; data latches 

CLRF

LATB

; Alternate method 

; to clear output 

; data latches 

MOVLW

0CFh

; Value used to

; initialize data 

; direction 

MOVWF

TRISB

; Set RB3:RB0 as inputs

; RB5:RB4 as outputs 

; RB7:RB6 as inputs 

Note 1: While in Low-Voltage ICSP mode, the

RB5 pin can no longer be used as a
general purpose I/O pin and should not
be held low during normal operation to
protect against inadvertent ICSP mode
entry.

2: When using Low-Voltage ICSP Program-

ming (LVP), the pull-up on RB5 becomes
disabled. If TRISB bit 5 is cleared,
thereby setting RB5 as an output, LATB
bit 5 must also be cleared for proper
operation.