Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 15
PIC18F97J94 FAMILY
FIGURE 1-2:
80-PIN DEVICE BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODL
PRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
12
3
PCLATU
PCU
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Control Signals
Decode
8
8
ROM Latch
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Precision
Reference
Band Gap
Regulator
Voltage
V
DDCORE
/V
CAP
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA<7:0>
(1,2)
RC<7:0>
(1)
RD<7:0>
(1)
RF<7:2>
(1)
RG<4:0>
(1)
PORTB
RB<7:0>
(1)
PORTH
RH<7:0>
(1)
PORTJ
RJ<7:0>
(1)
Note 1:
See
for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. See
for
more information.
Timing
Generation
INTRC
Oscillator
8 MHz
Oscillator
RE<7:0>
(1)
BOR and
HLVD
Data Memory
(4 Kbytes)
EUSART1
Comparator
MSSP1/2
3/5
2/4/6/8
CTMU
Timer1
A/D
12-Bit
EUSART2
Timer0
4/5/6/7/8/9/10
RTCC
Timer
Timer
1/2/3
CCP
ECCP
1/2/3
S
ystem
B
u
s I
n
ter
face
AD<15:0>, A<19:16>
(Multiplexed with PORTD,
PORTE and PORTH)
(Multiplexed with PORTD,
PORTE and PORTH)
USB
EUSART4 EUSART3
USB
USB
EMB
IR
LCD
352 Pixels