Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 159
PIC18F97J94 FAMILY
8.6.3
16-BIT BYTE SELECT MODE
shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
FIGURE 8-3:
16-BIT BYTE SELECT MODE EXAMPLE
AD<7:0>
AD<15:8>
ALE
373
A<20:1>
373
OE
WRH
A<19:16>
(2)
WRL
BA0
JEDEC Word
A<x:1>
D<15:0>
A<20:1>
CE
D<15:0>
I/O
OE WR
(1)
A0
BYTE/WORD
BYTE/WORD
FLASH Memory
JEDEC Word
A<x:1>
D<15:0>
CE
D<15:0>
OE WR
(1)
LB
UB
UB
SRAM Memory
LB
UB
138
(3)
Address Bus
Data Bus
Control Lines
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See
2:
Upper order address lines are used only for 20-bit address width.
3:
Demultiplexing is only required when multiple memory devices are accessed.
PIC18F97J94