Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 197
PIC18F97J94 FAMILY
11.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to eleven ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
enabled, there are up to eleven ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register, writes
to the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register, writes
to the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (putting the corresponding output
driver in a High-Impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding port pin an output (i.e.,
driver in a High-Impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding port pin an output (i.e.,
driving the contents of the corresponding LAT bit on the
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
OPERATION
11.1
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. All of the digital ports are
3.6V input tolerant.
port pins must be considered. All of the digital ports are
3.6V input tolerant.
11.1.1
OUTPUT PIN DRIVE
When used as digital I/O, the output pin drive strengths
vary, according to the pins’ grouping, to meet the needs
for a variety of applications. In general, there are two
classes of output pins in terms of drive capability:
• Outputs designed to drive higher current loads,
vary, according to the pins’ grouping, to meet the needs
for a variety of applications. In general, there are two
classes of output pins in terms of drive capability:
• Outputs designed to drive higher current loads,
such as LEDs:
- PORTB
- PORTC
- PORTB
- PORTC
• Outputs with lower drive levels, but capable of
driving normal digital circuit loads with a high input
impedance. Able to drive LEDs, but only those
with smaller current requirements:
- PORTA
impedance. Able to drive LEDs, but only those
with smaller current requirements:
- PORTA
- PORTD
- PORTE
- PORTF
- PORTG
- PORTH
(
)
- PORTJ
(
)
- PORTK
(
)
- PORTL
(
)
11.1.2
PULL-UP CONFIGURATION
Nine of the I/O ports (all ports except PORTA and
PORTC) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
Pull-ups for PORTB are enabled by clearing the RBPU
bit (INTCON2<7>). PORTB pull-ups are individually
selectable through the WPUB register.
Pull-ups for PORTD, PORTE, PORTF, PORTG,
PORTH, PORTJ, PORTK and PORTL are enabled
through their corresponding enable bits in the PADCFG
register, but are not pin-selectable.
PORTC) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
Pull-ups for PORTB are enabled by clearing the RBPU
bit (INTCON2<7>). PORTB pull-ups are individually
selectable through the WPUB register.
Pull-ups for PORTD, PORTE, PORTF, PORTG,
PORTH, PORTJ, PORTK and PORTL are enabled
through their corresponding enable bits in the PADCFG
register, but are not pin-selectable.
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
Buffer
I/O Pin
Q
D
CKx
Q
D
CKx
Q
D
EN
RD LAT
or PORT
Note 1: These ports are not available on 80-pin
devices.
2: These ports are not available on 80-pin or
100-pin devices.