Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 203
PIC18F97J94 FAMILY
11.3
PORTB, LATB and TRISB
Registers
Registers
PORTB is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only.
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 11-2:
INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>), and
setting the associated WPUB bit. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.
The RB<3:2> pins are multiplexed as CTMU edge
inputs.
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>), and
setting the associated WPUB bit. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.
The RB<3:2> pins are multiplexed as CTMU edge
inputs.
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
; to clear output
; data latches
MOVLW
0CFh
; Value used to
; initialize data
; direction
; initialize data
; direction
MOVWF
TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
TABLE 11-2:
PORTB FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/CTED13/
RP8/V
RP8/V
LCAP
1
RB0
0
O
DIG
LATB<0> data output.
1
I
ST
PORTB<0> data input.
INT0
1
I
ST
External Interrupt 0 input.
CTED13
1
I
ST
CTMU Edge 13 input.
RP8
x
x
DIG
Reconfigurable Pin 8 for PPS-Lite; TRIS must be set to match
input/output of module.
input/output of module.
V
LCAP
1
x
x
ANA
External capacitor connection for LCD module.
RB1/RP9/V
LCAP
2
RB1
0
O
DIG
LATB<1> data output.
1
I
ST
PORTB<1> data input.
RP9
x
x
DIG
Reconfigurable Pin 9 for PPS-Lite; TRIS must be set to match
input/output of module.
input/output of module.
V
LCAP
2
x
x
ANA
External capacitor connection for LCD module.
RB2/CTED1/RP14/
SEG9
SEG9
RB2
0
O
DIG
LATB<2> data output.
1
I
ST
PORTB<2> data input.
CTED1
1
I
ST
CTMU Edge 1 input.
RP14
x
x
DIG
Reconfigurable Pin 14 for PPS-Lite; TRIS must be set to match
input/output of module.
input/output of module.
SEG9
0
O
ANA
LCD Segment 9 output; disables all other pin functions.
RB3/CTED2/RP7/
SEG10
SEG10
RB3
0
O
DIG
LATB<3> data output.
1
I
ST
PORTB<3> data input.
CTED2
1
I
ST
CTMU Edge 2 input.
RP7
x
x
DIG
Reconfigurable Pin 7 for PPS-Lite; TRIS must be set to match
input/output of module.
input/output of module.
SEG10
0
O
ANA
LCD Segment 10 output; disables all other pin functions.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).