Microchip Technology DM183037 Data Sheet

 2012 Microchip Technology Inc.

DS30575A-page 209

PORTE is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.

Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, REPU (PADCFG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
For devices operating in Microcontroller mode, the RE7
pin can be configured as the alternate peripheral pin for
the ECCP2 module and Enhanced PWM Output 2A.

PORTE is also multiplexed with the Parallel Slave Port
address lines. RE2, RE1 and RE0 are multiplexed with
the control signals, CS, WR and RD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, see 

.

These pins are configured as digital inputs
on any device Reset.

CLRF

PORTE

; Initialize PORTE by
; clearing output
; data latches

CLRF

LATE

; Alternate method
; to clear output
; data latches

MOVLW

03h

; Value used to 
; initialize data 
; direction

MOVWF

TRISE

; Set RE<1:0> as inputs
; RE<7:2> as outputs

RE0//RD/RP28/
LCDBIAS1/AD8

RE0

0

O

DIG

LATE<0> data output.

1

I

ST

PORTE<0> data input.

RD

1

I

ST

Parallel Slave Port (PSP) Read (RD) signal.

RP28

x

x

DIG

Reconfigurable Pin 28 for PPS-Lite; TRIS must be set to match 
input/output of module.

LCDBIAS1

x

I

ANA

LCD Module Bias Voltage Input 1.

AD8

x

I/O

ST/DIG External Memory Bus Address Line 8.

RE1//WR/RP29/
LCDBIAS2/AD9

RE1

0

O

DIG

LATE<1> data output.

1

I

ST

PORTE<1> data input.

WR

1

I

ST

Parallel Slave Port (PSP) Write (WR) signal.

RP29

x

x

DIG

Reconfigurable Pin 29 for PPS-Lite; TRIS must be set to match 
input/output of module.

LCDBIAS2

x

I

ANA

LCD Module Bias Voltage Input 2.

AD9

x

I/O

ST/DIG External Memory Bus Address Line 9.

RE2/CS/RP30/
LCDBIAS3/AD10

RE2

0

O

DIG

LATE<2> data output.

1

I

ST

PORTE<2> data input.

CS

1

I

ST

Parallel Slave Port (PSP) Chip Select (CS) signal.

RP30

x

x

DIG

Reconfigurable Pin 30 for PPS-Lite; TRIS must be set to match 
input/output of module.

LCDBIAS3

x

I

ANA

LCD Module Bias Voltage Input 3.

AD10

x

I/O

ST/DIG External Memory Bus Address Line 10.

O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, 
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).