Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 253
PIC18F97J94 FAMILY
FIGURE 13-3:
LCD BIAS INTERNAL RESISTOR LADDER CONNECTION DIAGRAM
There are two power modes, designated as “Mode A”
and “Mode B”. Mode A is set by the LRLAP<1:0> bits
and Mode B by the LRLB<1:0> bits. The resistor ladder
to use for Modes A and B are selected by the bits,
LRLAP<1:0> and LRLBP<1:0>, respectively.
Each ladder has a matching contrast control ladder,
tuned to the nominal resistance of the reference ladder.
This contrast control resistor can be controlled by the
LCDCST<2:0> bits (LCDREFH<5:3>). Disabling the
internal reference ladder results in all of the ladders
being disconnected, allowing external voltages to be
supplied.
and “Mode B”. Mode A is set by the LRLAP<1:0> bits
and Mode B by the LRLB<1:0> bits. The resistor ladder
to use for Modes A and B are selected by the bits,
LRLAP<1:0> and LRLBP<1:0>, respectively.
Each ladder has a matching contrast control ladder,
tuned to the nominal resistance of the reference ladder.
This contrast control resistor can be controlled by the
LCDCST<2:0> bits (LCDREFH<5:3>). Disabling the
internal reference ladder results in all of the ladders
being disconnected, allowing external voltages to be
supplied.
To get additional current in High-Power mode, when
LRLAP<1:0> (LCDREFL<7:6>) = 11, both the medium
and high-power resistor ladders are activated.
Whenever the LCD module is inactive, LCDA
(LCDPS<5>) = 0), the reference ladder will be turned
off.
LRLAP<1:0> (LCDREFL<7:6>) = 11, both the medium
and high-power resistor ladders are activated.
Whenever the LCD module is inactive, LCDA
(LCDPS<5>) = 0), the reference ladder will be turned
off.
LCDBIAS3
LCDBIAS2
LCDBIAS1
VLCD3PE
VLCD2PE
VLCD1PE
LCDCST<2:0>
LCDIRE
LCDIRS
V
DD
3x Band Gap
LRLAT<2:0>
A Power Mode
B Power Mode
LRLAP<1:0>
LRLBP<1:0>
Low
Resistor
Ladder
Medium
Resistor
Ladder
High
Resistor
Ladder
V
DD
V
DDCORE