Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 262
2012 Microchip Technology Inc.
13.6.4
M3 (HARDWARE CONTRAST)
In M3, the LCD regulator is completely disabled. Like
M2, LCD bias levels are tied to V
M2, LCD bias levels are tied to V
DD
and are generated
using an external divider. The difference is that the
internal voltage reference is also disabled and the bot-
tom of the ladder is tied to ground (V
internal voltage reference is also disabled and the bot-
tom of the ladder is tied to ground (V
SS
. The value of the resistors, and the difference
between V
SS
and V
DD
, determine the contrast range;
no software adjustment is possible. This configuration
is also used where the LCD’s current requirements
exceed the capacity of the charge pump and software
contrast control is not needed.
Depending on the bias type required, resistors are con-
nected between some or all of the pins. A potentiome-
ter can also be connected between LCDBIAS3 and
V
exceed the capacity of the charge pump and software
contrast control is not needed.
Depending on the bias type required, resistors are con-
nected between some or all of the pins. A potentiome-
ter can also be connected between LCDBIAS3 and
V
DD
to allow for hardware controlled contrast adjust-
ment.
M3 is selected by clearing the CLKSEL<1:0> and
CPEN bits.
M3 is selected by clearing the CLKSEL<1:0> and
CPEN bits.
FIGURE 13-8:
RESISTOR LADDER CONNECTIONS FOR M3 CONFIGURATION
LCDBIAS3
Note 1: These values are provided for design guidance only; they should be optimized for the application by the
designer based on the actual LCD specifications.
2: A potentiometer for manual contrast adjustment is optional; it may be omitted entirely.
Bias Level at Pin
Bias Type
Static
1/2 Bias
1/3 Bias
LCDBIAS0
AV
SS
AV
SS
AV
SS
LCDBIAS1
AV
SS
1/2 V
DD
1/3 V
DD
LCDBIAS2
V
DD
1/2 V
DD
2/3 V
DD
LCDBIAS3
V
DD
V
DD
V
DD
10 k
(1)
10 k
(1)
Static Bias
1/2 Bias
1/3 Bias
LCDBIAS2
LCDBIAS1
LCDBIAS0
10 k
(1)
10 k
(1)
10 k
(1)
V
DD
(2)
V
DD
V
DD
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