Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 278
2012 Microchip Technology Inc.
13.13 LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame, which produces a visually crisp
transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for
segment data updates to the LCD frame.
A new frame is defined as beginning at the leading
edge of the COM0 common signal. The interrupt will be
set immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame, which produces a visually crisp
transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for
segment data updates to the LCD frame.
A new frame is defined as beginning at the leading
edge of the COM0 common signal. The interrupt will be
set immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
FINT
), as shown in
The LCD controller will begin to access data for the
next frame within the interval from the interrupt to when
the controller begins accessing data after the interrupt
(T
next frame within the interval from the interrupt to when
the controller begins accessing data after the interrupt
(T
FWR
). New data must be written within T
FWR
, as this
is when the LCD controller will begin to access the data
for the next frame.
for the next frame.
When the LCD driver is running with Type-B wave-
forms, and the LMUX<2:0> bits are not equal to ‘000’,
there are some additional issues.
Since the DC voltage on the pixel takes two frames to
maintain 0V, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform gener-
ated in the even frames and a DC component would be
introduced into the panel.
Because of this, using Type-B waveforms requires
synchronizing the LCD pixel updates to occur within a
subframe after the frame interrupt.
To correctly sequence writing in Type-B, the interrupt
only occurs on complete phase intervals. If the user
attempts to write when the write is disabled, the WERR
bit (LCDCON<5>) is set.
forms, and the LMUX<2:0> bits are not equal to ‘000’,
there are some additional issues.
Since the DC voltage on the pixel takes two frames to
maintain 0V, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform gener-
ated in the even frames and a DC component would be
introduced into the panel.
Because of this, using Type-B waveforms requires
synchronizing the LCD pixel updates to occur within a
subframe after the frame interrupt.
To correctly sequence writing in Type-B, the interrupt
only occurs on complete phase intervals. If the user
attempts to write when the write is disabled, the WERR
bit (LCDCON<5>) is set.
FIGURE 13-22:
EXAMPLE WAVEFORMS AND INTERRUPT TIMING IN QUARTER
DUTY CYCLE DRIVE
DUTY CYCLE DRIVE
Note:
The interrupt is not generated when the
Type-A waveform is selected and when
the Type-B with no multiplex (static) is
selected.
Type-A waveform is selected and when
the Type-B with no multiplex (static) is
selected.
Frame
Boundary
Frame
Boundary
LCD
Interrupt
Interrupt
Occurs
Controller Accesses
Next Frame Data
Next Frame Data
T
FINT
T
FWR
T
FWR
= T
FRAME
/2 * (LMUX<2:0> + 1) + T
CY
/2
T
FINT
= (T
FWR
/2 – (2 T
CY
+ 40 ns))
Minimum = 1.5(T
FRAME
/4) – (2 T
CY
+ 40 ns)
(T
FWR
/2 – (1 T
CY
+ 40 ns))
Maximum = 1.5(T
FRAME
/4) – (1 T
CY
+ 40 ns)
Frame
Boundary
V
3
V
2
V
1
V
0
V
3
V
2
V
1
V
0
V
3
V
2
V
1
V
0
V
3
V
2
V
1
V
0
COM0
COM1
COM2
COM3
2 Frames