Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 294
2012 Microchip Technology Inc.
16.0 TIMER2/4/6/8 MODULES
The Timer2/4/6/8 timer modules have the following
features:
• Eight-Bit Timer register (TMRx)
• Eight-Bit Period register (PRx)
• Readable and Writable (all registers)
• Software Programmable Prescaler (1:1, 1:4, 1:16)
• Software Programmable Postscaler (1:1 to 1:16)
• Interrupt on TMRx Match of PRx
features:
• Eight-Bit Timer register (TMRx)
• Eight-Bit Period register (PRx)
• Readable and Writable (all registers)
• Software Programmable Prescaler (1:1, 1:4, 1:16)
• Software Programmable Postscaler (1:1 to 1:16)
• Interrupt on TMRx Match of PRx
The Timer2/4/6/8 modules have a control register,
shown in
shown in
. Timer2/4/6/8 can be shut off by
clearing control bit, TMRxON (TxCON<2>), to minimize
power consumption. The prescaler and postscaler
selection of Timer2/4/6/8 also are controlled by this
register.
power consumption. The prescaler and postscaler
selection of Timer2/4/6/8 also are controlled by this
register.
is a simplified block diagram of the
Timer2/4/6/8 modules.
16.1
Timer2/4/6/8 Operation
Timer2/4/6/8 can be used as the PWM time base for
the PWM mode of the ECCP modules. The TMRx reg-
isters are readable and writable, and are cleared on
any device Reset. The input clock (F
the PWM mode of the ECCP modules. The TMRx reg-
isters are readable and writable, and are cleared on
any device Reset. The input clock (F
OSC
/4) has a
prescale option of 1:1, 1:4 or 1:16, selected by control
bits, TxCKPS<1:0> (TxCON<1:0>). The match output
of TMRx goes through a four-bit postscaler (that gives
a 1:1 to 1:16 inclusive scaling) to generate a TMRx
interrupt, latched in the flag bit, TMRxIF.
bits, TxCKPS<1:0> (TxCON<1:0>). The match output
of TMRx goes through a four-bit postscaler (that gives
a 1:1 to 1:16 inclusive scaling) to generate a TMRx
interrupt, latched in the flag bit, TMRxIF.
gives each module’s flag bit.
The interrupt can be enabled or disabled by setting or
clearing the Timerx Interrupt Enable bit (TMRxIE),
shown in
clearing the Timerx Interrupt Enable bit (TMRxIE),
shown in
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMRx register
• A write to the TxCON register
• Any device Reset – Power-on Reset (POR),
when any of the following occurs:
• A write to the TMRx register
• A write to the TxCON register
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
Brown-out Reset (BOR)
A TMRx is not cleared when a TxCON is written.
Note: Throughout this section, generic references
are used for register and bit names that are the
same, except for an ‘x’ variable that indicates
the item’s association with the Timer2, Timer4,
Timer6 or Timer8 module. For example, the
control register is named TxCON and refers to
T2CON, T4CON, T6CON and T8CON.
same, except for an ‘x’ variable that indicates
the item’s association with the Timer2, Timer4,
Timer6 or Timer8 module. For example, the
control register is named TxCON and refers to
T2CON, T4CON, T6CON and T8CON.
TABLE 16-1:
TIMER2/4/6/8 FLAG BITS
Timer Module
Flag Bit
2
PIR1<1>
4
PIR5<0>
6
PIR5<2>
8
PIR5<4>
TABLE 16-2:
TIMER2/4/6/8 INTERRUPT
ENABLE BITS
ENABLE BITS
Timer Module
Flag Bit
2
PIE1<1>
4
PIE5<0>
6
PIE5<2>
8
PIE5<4>
Note:
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see
,
and
.