Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 339
PIC18F97J94 FAMILY
19.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F97J94 family devices have seven CCP
(Capture/Compare/PWM) modules, designated CCP4
through CCP10. All the modules implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
(Capture/Compare/PWM) modules, designated CCP4
through CCP10. All the modules implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
Each CCP module contains a 16-bit register that can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP4,
but is equally applicable to CCP5 through CCP10.
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP4,
but is equally applicable to CCP5 through CCP10.
Note:
Throughout this section, generic references
are used for register and bit names that are
the same, except for an ‘x’ variable that indi-
cates the item’s association with the specific
CCP module. For example, the control
register is named CCPxCON and refers to
CCP4CON through CCP10CON.
are used for register and bit names that are
the same, except for an ‘x’ variable that indi-
cates the item’s association with the specific
CCP module. For example, the control
register is named CCPxCON and refers to
CCP4CON through CCP10CON.
REGISTER 19-1:
CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
(
1
)
CCPxM2
(
1
)
CCPxM1
(
1
)
CCPxM0
(
1
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx module bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Module Mode Select bits
(
1
)
0000 = Capture/Compare/PWM is disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggles output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: Every falling edge
0101 = Capture mode: Every rising edge
0110 = Capture mode: Every 4th rising edge
0111 = Capture mode: Every 16th rising edge
1000 = Compare mode: Initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: Initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: Generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
0001 = Reserved
0010 = Compare mode, toggles output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: Every falling edge
0101 = Capture mode: Every rising edge
0110 = Capture mode: Every 4th rising edge
0111 = Capture mode: Every 16th rising edge
1000 = Compare mode: Initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: Initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: Generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: Special Event Trigger; reset timer on CCPx match
(CCPxIF bit is set)
11xx = PWM mode
Note 1:
CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on a CCPx match.