Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 357
PIC18F97J94 FAMILY
20.3.4
ENABLING SPI I/O
To enable the serial port, the peripheral must first be
mapped to I/O pins using the PPS-Lite feature. To
enable the SPI peripheral, the MSSPx Enable bit,
SSPEN (SSPxCON1<5>) must be set. To reset or
reconfigure SPI mode, clear the SSPEN bit, re-initialize
the SSPxCON registers and then set the SSPEN bit.
This configures the SDIx, SDOx, SCKx and SSx pins
as serial port pins. For the pins to behave as the serial
port function, some must have their data direction bits
(in the TRIS register) appropriately programmed as
follows:
• SDIx is automatically controlled by the SPI
mapped to I/O pins using the PPS-Lite feature. To
enable the SPI peripheral, the MSSPx Enable bit,
SSPEN (SSPxCON1<5>) must be set. To reset or
reconfigure SPI mode, clear the SSPEN bit, re-initialize
the SSPxCON registers and then set the SSPEN bit.
This configures the SDIx, SDOx, SCKx and SSx pins
as serial port pins. For the pins to behave as the serial
port function, some must have their data direction bits
(in the TRIS register) appropriately programmed as
follows:
• SDIx is automatically controlled by the SPI
module
• SDOx must have the TRIS bit cleared for the
corresponding RPn pin.
• SCKx (Master mode) must have the TRIS bit
cleared for the corresponding RPn pin
• SCKx (Slave mode) must have the TRIS bit set
for the corresponding RPn pin
• SSx must have the TRIS bit set for the
corresponding RPn pin.
Any serial port function that is not desired may be
overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
20.3.5
TYPICAL CONNECTION
shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data
–Slave sends dummy data
• Master sends data
–Slave sends data
• Master sends dummy data
–Slave sends data
FIGURE 20-2:
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master SSPM<3:0> = 00xxb
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2
SCKx
SPI Slave SSPM<3:0> =
010x
b
Serial Clock