Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 361
PIC18F97J94 FAMILY
20.3.9
OPERATION IN POWER-MANAGED
MODES
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode. In
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (SOSC Oscillator) or the INTOSC
source.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSPx interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes,
when the master completes sending data. If an exit
from Sleep or Idle mode is not desired, MSSPx
interrupts should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSPx interrupt flag bit will be set, and if
enabled, will wake the device.
at a different speed than when in full-power mode. In
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (SOSC Oscillator) or the INTOSC
source.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSPx interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes,
when the master completes sending data. If an exit
from Sleep or Idle mode is not desired, MSSPx
interrupts should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSPx interrupt flag bit will be set, and if
enabled, will wake the device.
20.3.10
EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates
the current transfer.
the current transfer.
20.3.11
BUS MODE COMPATIBILITY
shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
CKE control bits.
TABLE 20-1:
SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
is sampled.
20.3.12
SPI CLOCK SPEED AND MODULE
INTERACTIONS
INTERACTIONS
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM<3:0> bits of the
SSPxCON1 register determines the rate for the
corresponding module.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 module’s operation will affect
both MSSPx modules equally. If different bit rates are
required for each module, the user should select one of
the other three time base options for one of the
modules.
modules, they can operate simultaneously at different
data rates. Setting the SSPM<3:0> bits of the
SSPxCON1 register determines the rate for the
corresponding module.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 module’s operation will affect
both MSSPx modules equally. If different bit rates are
required for each module, the user should select one of
the other three time base options for one of the
modules.
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0