Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 364
2012 Microchip Technology Inc.
REGISTER 20-4:
DMACON1: DMA CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSCON1
SSCON0
TXINC
RXINC
DUPLEX1
DUPLEX0
DLYINTEN
DMAEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
SSCON<1:0>: SSDMA Output Control bits (Master modes only)
11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low
01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low
10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low
00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable
11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low
01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low
10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low
00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable
bit 5
TXINC: Transmit Address Increment Enable bit
Allows the transmit address to increment as the transfer progresses.
1 = The transmit address is to be incremented from the initial value of TXADDR<11:0>
0 = The transmit address is always set to the initial value of TXADDR<11:0>
Allows the transmit address to increment as the transfer progresses.
1 = The transmit address is to be incremented from the initial value of TXADDR<11:0>
0 = The transmit address is always set to the initial value of TXADDR<11:0>
bit 4
RXINC: Receive Address Increment Enable bit
Allows the receive address to increment as the transfer progresses.
1 = The received address is to be incremented from the initial value of RXADDR<11:0>
0 = The received address is always set to the initial value of RXADDR<11:0>
Allows the receive address to increment as the transfer progresses.
1 = The received address is to be incremented from the initial value of RXADDR<11:0>
0 = The received address is always set to the initial value of RXADDR<11:0>
bit 3-2
DUPLEX<1:0>: Transmit/Receive Operating Mode Select bits
10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received
01 = DMA operates in Half-Duplex mode, data is transmitted only
00 = DMA operates in Half-Duplex mode, data is received only
10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received
01 = DMA operates in Half-Duplex mode, data is transmitted only
00 = DMA operates in Half-Duplex mode, data is received only
bit 1
DLYINTEN: Delay Interrupt Enable bit
Enables the interrupt to be invoked after the number of T
Enables the interrupt to be invoked after the number of T
CY
cycles, specified in DLYCYC<3:0>, has
elapsed from the latest completed transfer.
1 = The interrupt is enabled, SSCON<1:0> must be set to ‘00’
0 = The interrupt is disabled
1 = The interrupt is enabled, SSCON<1:0> must be set to ‘00’
0 = The interrupt is disabled
bit 0
DMAEN: DMA Operation Start/Stop bit
This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA
engine when the DMA operation is completed or aborted.
1 = DMA is in session
0 = DMA is not in session
This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA
engine when the DMA operation is completed or aborted.
1 = DMA is in session
0 = DMA is not in session