Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 395
PIC18F97J94 FAMILY
20.5.9
MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPMx bits in SSPxCON1, and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSPx hardware if the
TRIS bits are set.
The Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSPx module is disabled.
Control of the I
appropriate SSPMx bits in SSPxCON1, and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSPx hardware if the
TRIS bits are set.
The Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSPx module is disabled.
Control of the I
2
C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
In Firmware Controlled Master mode, user code
conducts all I
2
C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
Once Master mode is enabled, the user has six
options.
1.
Assert a Start condition on SDAx and SCLx.
2.
Assert a Repeated Start condition on SDAx and
SCLx.
SCLx.
3.
Write to the SSPxBUF register initiating
transmission of data/address.
transmission of data/address.
4.
Configure the I
2
C port to receive data.
5.
Generate an Acknowledge condition at the end
of a received byte of data.
of a received byte of data.
6.
Generate a Stop condition on SDAx and SCLx.
The following events will cause the MSSPx Interrupt
Flag bit, SSPxIF, to be set (and MSSPx interrupt if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
Flag bit, SSPxIF, to be set (and MSSPx interrupt if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
FIGURE 20-18:
MSSPx BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Note:
The MSSPx module, when configured in
I
I
2
C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
Read
Write
SSPxSR
Start bit, Stop bit,
SSPxBUF
Internal
Data Bus
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1);
Shift
Clock
MSb
LSb
SDAx
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCLx
SCLx In
Bus Collision
SDAx In
Receive Enable
Cloc
k Cnt
l
Clock
A
rbit
rat
e/
W
C
O
L
Det
e
ct
(hold
of
f clock sour
ce)
SSPxADD<6:0>
Baud
Set SSPxIF, BCLxIF;
Reset ACKSTAT, PEN (SSPxCON2)
Reset ACKSTAT, PEN (SSPxCON2)
Rate
Generator
SSPM<3:0>
Start bit Detect