Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 42
2012 Microchip Technology Inc.
REGISTER 3-2:
OSCCON2: OSCILLATOR CONTROL REGISTER 2
R/W-0
R/W-0
R-0
U-0
R/C-0
R/W-0
R/W-0
U-0
CLKLOCK
(
IOLOCK
(
LOCK
—
CF
POSCEN
SOSCGO
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CLKLOCK: Clock Lock Enabled bit
)
1 = Clock and PLL selection are locked and may not be modified
0 = Clock and PLL selection are not locked, configurations may be modified
0 = Clock and PLL selection are not locked, configurations may be modified
bit 6
IOLOCK: I/O Lock Enable bit
1 = I/O lock is active (If IOL1WAY (CONFIG5H<0> = 1), the bit cannot be cleared, once it is set, except
on a device Reset.)
0 = I/O lock is not active
bit 5
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL module is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL module is out of lock, PLL start-up timer is in progress or PLL is disabled
1 = Indicates that PLL module is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL module is out of lock, PLL start-up timer is in progress or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit (readable/clearable by application)
1 = FSCM has detected a clock failure
0 = FSCM has not detected A clock failure
1 = FSCM has detected a clock failure
0 = FSCM has not detected A clock failure
bit 2
POSCEN: Primary Oscillator (POSC) Enable bit
1 = Enables Primary Oscillator in Sleep mode
0 = Disables Primary Oscillator in Sleep mode
1 = Enables Primary Oscillator in Sleep mode
0 = Disables Primary Oscillator in Sleep mode
bit 1
SOSCGO: 32 kHz Secondary (LP) Oscillator Enable bit
1 = Enables Secondary Oscillator independent of other SOSC enable requests; provides a way to keep
1 = Enables Secondary Oscillator independent of other SOSC enable requests; provides a way to keep
the SOSC running even when not actively used by the system
0 = Disables Secondary Oscillator; the SOSC will be enabled if directly requested by the system. Reset
on POR or BOR only.
bit 0
Unimplemented: Read as ‘0’
Note 1:
The IOLOCK bit cannot be cleared once it has been set, provided that the IOL1WAY (CONFIG5H<0>) = 1.
2:
If the user wants to change the clock source, ensure that the FSCM<1:0> bits (CONFIG3L<5:4>) are set
appropriately.
appropriately.