Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 458
2012 Microchip Technology Inc.
22.3
A/D Module Configuration
All of the registers described in the previous section
must be configured for module operation to be fully
defined. An effective approach is first, to describe the
signals and sequences for the particular application.
Typically, it is an iterative process to assign signals to
must be configured for module operation to be fully
defined. An effective approach is first, to describe the
signals and sequences for the particular application.
Typically, it is an iterative process to assign signals to
port pins, to establish timing methods and to organize
a scanning scheme, as well as to integrate the whole
process with the software design.
The various configuration and control functions of the
module are distributed throughout the module's six
control registers. Control functions can be broadly
sorted into four groups: input, timing, conversion and
output.
a scanning scheme, as well as to integrate the whole
process with the software design.
The various configuration and control functions of the
module are distributed throughout the module's six
control registers. Control functions can be broadly
sorted into four groups: input, timing, conversion and
output.
shows the register location of control
or status bits by register.
TABLE 22-1:
A/D MODULE FUNCTIONS BY REGISTERS AND BITS
The following steps should be followed for performing
an A/D conversion:
1.
an A/D conversion:
1.
Configure the A/D module:
- Select the output resolution (if configurable)
- Select the voltage reference source to match
- Select the voltage reference source to match
the expected range on analog inputs
- Select the analog conversion clock to match
the desired data rate with a processor clock
- Determine how sampling will occur
- Set the multiplexer input assignments
- Select the desired sample/conversion
- Set the multiplexer input assignments
- Select the desired sample/conversion
sequence
- Select the output data format
- Select the output value destination
- Select the number of readings per interrupt
- Select the output value destination
- Select the number of readings per interrupt
2.
Configure the A/D interrupt (if required):
- Clear the ADIF bit
- Select the A/D interrupt priority
- Select the A/D interrupt priority
3.
Turn on the A/D module.
The options for each configuration step are described
in the subsequent sections.
in the subsequent sections.
22.3.1
SELECTING THE RESOLUTION
The MODE12 bit (ADCON1H<3>) controls output
resolution. Setting this bit selects 12-bit resolution.
resolution. Setting this bit selects 12-bit resolution.
22.3.2
SELECTING THE VOLTAGE
REFERENCE SOURCE
REFERENCE SOURCE
The voltage references for A/D conversions are
selected using the PVCFG<1:0> and NVCFG0 control
bits (ADCON2H<7:5>). The upper voltage reference
(VR+) may be AV
selected using the PVCFG<1:0> and NVCFG0 control
bits (ADCON2H<7:5>). The upper voltage reference
(VR+) may be AV
DD
, the external V
REF
+ or an internal
band gap reference voltage. The lower voltage
reference (VR-) may be AV
reference (VR-) may be AV
SS
or the V
REF
- input pin.
The available options vary between device families.
The external voltage reference pins may be shared
with the AN0 and AN1 inputs on low pin count devices.
The A/D Converter can still perform conversions on
these pins when they are shared with the V
The external voltage reference pins may be shared
with the AN0 and AN1 inputs on low pin count devices.
The A/D Converter can still perform conversions on
these pins when they are shared with the V
REF
+ and
V
REF
- input pins.
The voltages applied to the external reference pins
must meet certain specifications. Refer to the device
data sheet for further details.
must meet certain specifications. Refer to the device
data sheet for further details.
A/D Function
Register(s)
Specific Bits
Input
AD1CON2
PVCFG<1:0>, NVCFG, OFFCAL, CSCNA, ALTS
AD1CON5
CTMREQ, BGREQ, VRSREQ
AD1CHS
CH0NB<2:0>, CH0SB<4:0>, CH0NA<2:0>, CH0SA<4:0>
AD1CSSH/L
CSS<31:16>, CSS<15:0>
(
1
)
AD1CTMENH/L
CTMEN<31:16>, CTMEN<15:0>
(
1
)
Conversion
AD1CON1
ADON, ADSIDL, SSRC<3:0>, ASAM, SAMP, DONE
AD1CON2
SMPI<4:0>
AD1CON3
EXTSAM
AD1CON5
ASEN, LPEN, ASINT<1:0>
Timing
AD1CON3
ADRC, SAMC<4:0>, ADCS<7:0>
Output
AD1CON1
FORM<1:0>, DMAEN, DMABM
AD1CON2
BUFS, BUFM, BUFREGEN
AD1CON4
DMABL<2:0>
AD1CON5
WM<1:0>, CM<1:0>
Note:
Do not write to the SSRCx, BUFS, SMPIx,
BUFM and ALTS bits, or the AD1CON3
and AD1CSSL registers, while ADON = 1;
otherwise, indeterminate conversion data
may result.
BUFM and ALTS bits, or the AD1CON3
and AD1CSSL registers, while ADON = 1;
otherwise, indeterminate conversion data
may result.