Microchip Technology DM183037 Data Sheet

 2012 Microchip Technology Inc.

DS30575A-page 485

The Analog Input model of the 12-bit A/D Converter is
shown in 

. The total sampling time for the

A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The source impedance (RS), the interconnect
impedance (RIC) and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge CHOLD. The combined impedance
of the analog sources must, therefore, be small enough

to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D Converter, the
maximum recommended source impedance, RS, is 2.5
k. After the analog input channel is selected (changed),
this sampling function must be completed prior to
starting the conversion. The internal holding capacitor
will be in a discharged state prior to each sample
operation.
At least 1 TAD time period should be allowed between
conversions for the sample time. For more details, see

The transfer functions of the A/D Converter, in 12-bit
and 10-bit resolution, are shown in 

 and

, respectively. In both cases, the differ-

ence of the input voltages, (VINH - VINL), is compared
to the reference, ((VR+) - (VR-)).

For the 12-bit transfer function:
• The first code transition occurs when the input 

voltage is ((VR+) - (VR-))/4096 or 1.0 LSb.

• The  '0000 0000 0001' code is centered at VR- 

+ (1.5 * ((VR+) - (VR-)) / 4096).

• The  '0010 0000 0000' code is centered at 

VREFL + (2048.5 * ((VR+) - (VR-)) /4096).

• An input voltage less than VR- + (((VR-) - (VR-)) / 

4096) converts as '0000 0000 0000'.

• An input voltage greater than (VR-) + (4096 

((VR+) - (VR-))/4096) converts as '1111 1111 
1111'.

C

PIN

VA

Rs

ANx

I

LEAKAGE

R

IC

 

 250

Sampling

Switch

R

SS

C

HOLD

V

SS

= 4.4 pF

500 nA

Legend: C

PIN

V

T

I

LEAKAGE

R

IC

R

SS

C

HOLD

= Input Capacitance
= Threshold Voltage
= Leakage Current at the Pin due to

= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)

Various Junctions

Note: C

PIN

 value depends on device package and is not tested. The effect of the C

PIN

 is negligible if Rs 

 5 k.

R

SS

 

 3 k