Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 534
2012 Microchip Technology Inc.
27.4
Buffer Descriptors and the Buffer
Descriptor Table
Descriptor Table
The registers in Bank 13 are used specifically for end-
point buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four
registers, where n represents one of the 64 possible
BDs (range of 0 to 63):
• BDnSTAT: BD Status Register
• BDnCNT: BD Byte Count Register
• BDnADRL: BD Address Low Register
• BDnADRH: BD Address High Register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1, in hexa-
decimal) from D00h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(
point buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four
registers, where n represents one of the 64 possible
BDs (range of 0 to 63):
• BDnSTAT: BD Status Register
• BDnCNT: BD Byte Count Register
• BDnADRL: BD Address Low Register
• BDnADRH: BD Address High Register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1, in hexa-
decimal) from D00h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(
), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB Specification mandates that every device
must have Endpoint 0 with both input and output for ini-
tial setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint cor-
responding to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
the BDT must be at least 8 bytes long. This is because
the USB Specification mandates that every device
must have Endpoint 0 with both input and output for ini-
tial setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint cor-
responding to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
provides an example of a BD for a 64-byte
buffer, starting at 500h. A particular set of BD registers
is only valid if the corresponding endpoint has been
enabled using the UEPn register. All BD registers are
available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
is only valid if the corresponding endpoint has been
enabled using the UEPn register. All BD registers are
available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
27.4.1
BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an end-
point buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
point buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
FIGURE 27-5:
EXAMPLE OF A BUFFER
DESCRIPTOR
DESCRIPTOR
Unlike other control registers, the bit configuration for
the BDnSTAT register is context-sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
the BDnSTAT register is context-sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
27.4.1.1
Buffer Ownership
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can
configure the basic operation of the peripheral through
the BDnSTAT bits. During this time, the byte count and
buffer location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can
configure the basic operation of the peripheral through
the BDnSTAT bits. During this time, the byte count and
buffer location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
D00h
USB Data
Buffer
Buffer
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
D01h
D02h
D03h
D02h
D03h
500h
53Fh
Descriptor
Note:
Memory regions are not to scale.
40h
00h
05h
00h
05h
Starting
Size of Block
(xxh)
Registers
Address
Contents
Address