Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 58
2012 Microchip Technology Inc.
3.13.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit must be programmed to ‘0’. If the FCKSM1 Config-
uration bit is unprogrammed (‘1’), the clock switching
function and Fail-Safe Clock Monitor function are
disabled; this is the default setting.
The NOSCx control bits (OSCCON<2:0>) do not control
the clock selection when clock switching is disabled. How-
ever, the COSCx bits (OSCCON<6:4>) will reflect the
clock source selected by the FOSC Configuration bits.
bit must be programmed to ‘0’. If the FCKSM1 Config-
uration bit is unprogrammed (‘1’), the clock switching
function and Fail-Safe Clock Monitor function are
disabled; this is the default setting.
The NOSCx control bits (OSCCON<2:0>) do not control
the clock selection when clock switching is disabled. How-
ever, the COSCx bits (OSCCON<6:4>) will reflect the
clock source selected by the FOSC Configuration bits.
3.13.2
OSCILLATOR SWITCHING
SEQUENCE
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1.
basic sequence:
1.
If desired, read the COSCx bits (OSCCON<6:4>)
to determine the current oscillator source.
to determine the current oscillator source.
2.
Clear the CLKLOCK bit (OSCCON2<7>) to
enable writes to the NOSCx bits (OSCCON<2:0>).
enable writes to the NOSCx bits (OSCCON<2:0>).
3.
Write the appropriate value to the NOSCx control
bits (OSCCON<2:0>) for the new oscillator
source.
bits (OSCCON<2:0>) for the new oscillator
source.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
clock hardware responds automatically as follows:
1.
The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. If they are
different, then a valid clock switch has been
initiated.
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. If they are
different, then a valid clock switch has been
initiated.
2.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
3.
The hardware waits for the new clock source to
stabilize and then performs the clock switch.
stabilize and then performs the clock switch.
4.
The hardware clears the OSWEN bit to indicate
a successful clock transition has occurred.
a successful clock transition has occurred.
5.
The NOSCx bit values are transferred to the
COSCx status bits.
COSCx status bits.
6.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled) or SOSC (if it is enabled by one of the
timer sources).
with the exception of LPRC (if WDT or FSCM is
enabled) or SOSC (if it is enabled by one of the
timer sources).
The timing of the transition between clock sources is
shown in
shown in
.
FIGURE 3-9:
CLOCK TRANSITION TIMING DIAGRAM
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
sequence. Timing-sensitive code should
not be executed during this time.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
Old Clock Source
New Clock Source
System Clock
Both Oscillators Active
New Source
Enabled
New Source
Stable
Old Source
Disabled
Note: The system clock can be any selected source (Primary, Secondary, FRC or LPRC).
NOSC = COSC
(old oscillator enabled)
NOSC ≠ COSC
(oscillator source in process of transition)
NOSC = COSC
(new oscillator
source enabled)