Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS3
0575A-page
66
20
12 M
12 M
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rochip
T
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In
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TABLE 4-1:
SUMMARY OF OPERATING MODES FOR PIC18F97J94 FAMILY DEVICES WITH V
BAT
POWER-SAVING FEATURES
Mode
Entry
Active Systems
Exit Conditions
Interrupts
Resets
RT
CC Alarm
(DS)
W
D
T
(
)
V
DD
R
esto
re
Code Execution
Resumes
Co
re
P
e
ri
p
h
e
ral
s
Dat
a
R
A
M
Reten
tio
n
RT
C
C
)
DS
GP
Rx
(
)
All
INT0
Onl
y
All
PO
R
MCL
R
Run (default)
N/A
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Idle
Instruction
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N/A
Next Instruction
Sleep modes:
Sleep
Instruction
N
N
(
)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N/A
Next Instruction
Retention
Sleep
Sleep
Instruction +
RETEN bit
N
N
(
)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N/A
Deep Sleep modes:
Retention
Deep Sleep
Deep Sleep
Instruction +
DSEN bit +
RETEN bit
N
N
Y
Y
Y
N
Y
N
Y
Y
Y
Y
N/A
Next Instruction
Deep Sleep
Instruction +
DSEN bit
N
N
N
Y
Y
N
Y
N
Y
Y
Y
Y
N/A
Reset Vector
V
BAT
:
with RTCC
with RTCC
Hardware
N
N
N
Y
Y
N
N
N
N
N
N
N
Y
Reset Vector
w/o RTCC
Hardware +
by disabling the
RTCC PMD bit
N
N
N
N
Y
N
N
N
N
N
N
N
Y
Note 1:
If RTCC is otherwise enabled in firmware.
2:
Data retention in the DSGPR0, DSGPR1, DSGPR2 and DSGPR3 registers.
3:
Deep Sleep WDT in Deep Sleep modes; WDT in all other modes.
4:
Some select peripherals may continue to operate in this mode, using either the LPRC or an external clock source.