Microchip Technology DM183037 Data Sheet

Microchip Technology

 2012 Microchip Technology Inc.

DS30575A-page 687

PIC18F97J94 FAMILY

Associated Alarm Value Registers ........................... 316
Associated Control Registers ................................... 316
Associated Value Registers ..................................... 316
Control Registers ..................................................... 299
Operation ................................................................. 310

Calibration ........................................................ 313
Clock Source  ................................................... 311
Digit Carry Rules .............................................. 311
General Functionality  ....................................... 312
Leap Year  ........................................................ 312
Register Mapping ............................................. 312

ALRMVAL ................................................ 313
RTCVAL ................................................... 312

Safety Window for Register Reads and Writes 312
Write Lock ........................................................ 312

Register Interface ..................................................... 310
Register Maps .......................................................... 316
Reset ........................................................................ 315

Device .............................................................. 315
Power-on Reset (POR) .................................... 315

RTCEN Bit Write ...................................................... 310
Sleep Mode .............................................................. 315
Value Registers (RTCVAL) ...................................... 303

S

Secondary Oscillator (SOSC) ............................................ 55

Enabling ..................................................................... 55

Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 609
Shoot-Through Current .................................................... 333
SLEEP ............................................................................. 610
Sleep Mode

Delay Times for Exit (table) ........................................ 70

Software Simulator (MPLAB SIM) .................................... 627
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Mode).
SPI Mode (MSSP) ............................................................ 352

Bus Mode Compatibility  ........................................... 361
Clock Speed, Interactions  ........................................ 361
DMA Module  ............................................................ 362

I/O Pin Considerations  ..................................... 362
Idle, Sleep Considerations  ............................... 362
RAM to RAM Copy Operations  ........................ 362
Registers .......................................................... 362

Effects of a Reset ..................................................... 361
Enabling SPI I/O  ...................................................... 357
Master Mode  ............................................................ 358
Master/Slave Connection ......................................... 357
Operation ................................................................. 356
Operation in Power-Managed Modes  ...................... 361
Slave Mode  .............................................................. 359
Slave Select Synchronization  .................................. 359
SPI Clock  ................................................................. 358
SSPxBUF Register  .................................................. 358
SSPxSR Register ..................................................... 358
Typical Connection  .................................................. 357

SSPOV ............................................................................. 401
SSPOV Status Flag ......................................................... 401
SSPxSTAT Register

R/W Bit ............................................................. 380, 383

ST

Block Diagram ............................................................ 60

Stack Full/Underflow Resets ............................................ 117
SUBFSR .......................................................................... 621
SUBFWB .......................................................................... 610
SUBLW ............................................................................ 611

SUBULNK ........................................................................ 621
SUBWF ............................................................................ 611
SUBWFB ......................................................................... 612
SWAPF ............................................................................ 612

T

Table Reads/Table Writes ............................................... 117
TBLRD ............................................................................. 613
TBLWT ............................................................................ 614
Timer0 ............................................................................. 281

Operation ................................................................. 282
Overflow Interrupt .................................................... 283
Prescaler ................................................................. 283

Switching Assignment ..................................... 283

Prescaler Assignment (PSA Bit) .............................. 283
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 283
Reads and Writes in 16-Bit Mode ............................ 282

Timer1/3/5 ....................................................................... 284

16-Bit Read/Write Mode  .......................................... 288
Gates ....................................................................... 289
Operation ................................................................. 287
Oscillator .................................................................. 284
Overflow Interrupt  ............................................ 284, 293
Special Event Trigger (ECCP) ................................. 293
TMRxH Register  ...................................................... 284
TMRxL Register ....................................................... 284
Using SOSC Oscillator as Clock Source  ................. 288

Timer2

PR2 Register ........................................................... 348
TMR2 to PR2 Match Interrupt .................................. 348

Timer2/4/6/8 .................................................................... 294

Interrupt ................................................................... 295
MSSP Clock Shift .................................................... 295
Operation ................................................................. 294
Output ...................................................................... 295
Postscaler. See Postscaler, Timer2/4/6/8.
Prescaler. See Prescaler, Timer2/4/6/8.
PRx Register ........................................................... 294
TMRx Register ......................................................... 294

Timing Diagrams

’0’ Bit Data IrDA Encoding Scheme  ......................... 432
A/D Conversion  ....................................................... 661
Asynchronous Reception ......................................... 424
Asynchronous Transmission  ................................... 422
Asynchronous Transmission (Back-to-Back) ........... 422
Automatic Baud Rate Calculation ............................ 420
Auto-Sample Start, Conversion Trigger Based

Conversion Start .............................................. 465

Auto-Wake-up Bit (WUE) During Normal Operation  425
Auto-Wake-up Bit (WUE) During Sleep ................... 425
Baud Rate Generator with Clock Arbitration ............ 398
BCLK Output vs. BRG Programming  ...................... 431
BRG Overflow Sequence  ........................................ 420
BRG Reset Due to SDAx Arbitration During

Start Condition ................................................. 407

Brown-out Reset (BOR) ........................................... 647
Bus Collision During Repeated Start Condition

(Case 1) ........................................................... 408

Bus Collision During Repeated Start Condition

(Case 2) ........................................................... 408

Bus Collision During Start Condition (SCLx = 0)  ..... 407
Bus Collision During Start Condition (SDAx Only)  .. 406
Bus Collision During Stop Condition (Case 1) ......... 409
Bus Collision During Stop Condition (Case 2) ......... 409
Bus Collision for Transmit and Acknowledge  .......... 405
Capture/Compare/PWM (CCP1, CCP2) .................. 650