Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 69
PIC18F97J94 FAMILY
4.2.4.1
Retention Sleep Mode
Retention Sleep mode allows for additional power sav-
ings over Sleep mode by maintaining key systems from
the lower power retention regulator. When the retention
regulator is used, the normal on-chip voltage regulator
(operating at 1.8V nominal) is turned off and will enable
a low-power (1.2V typical) regulator. By using a lower
voltage, a lower total power consumption is achieved.
Retention Sleep also offers the advantage of maintain-
ing the contents of the data RAM. As a trade-off, the
wake-up time is longer than that for Sleep mode.
Retention Sleep mode is controlled by the SRETEN bit
(RCON4<4>) and the RETEN Configuration bit, as
described in
ings over Sleep mode by maintaining key systems from
the lower power retention regulator. When the retention
regulator is used, the normal on-chip voltage regulator
(operating at 1.8V nominal) is turned off and will enable
a low-power (1.2V typical) regulator. By using a lower
voltage, a lower total power consumption is achieved.
Retention Sleep also offers the advantage of maintain-
ing the contents of the data RAM. As a trade-off, the
wake-up time is longer than that for Sleep mode.
Retention Sleep mode is controlled by the SRETEN bit
(RCON4<4>) and the RETEN Configuration bit, as
described in
.
4.3
Clock Source Considerations
When the device wakes up from either of the Sleep
modes, it will restart the same clock source that was
active when Sleep mode was entered. Wake-up delays
for the different oscillator modes are shown in
modes, it will restart the same clock source that was
active when Sleep mode was entered. Wake-up delays
for the different oscillator modes are shown in
and
, respectively.
If the system clock source is derived from a crystal oscil-
lator and/or the PLL, the Oscillator Start-up Timer (OST)
and/or PLL lock times must be applied before the system
clock source is made available to the device. As an
exception to this rule, no oscillator delays are necessary
if the system clock source is the Secondary Oscillator
and it was running while in Sleep mode.
lator and/or the PLL, the Oscillator Start-up Timer (OST)
and/or PLL lock times must be applied before the system
clock source is made available to the device. As an
exception to this rule, no oscillator delays are necessary
if the system clock source is the Secondary Oscillator
and it was running while in Sleep mode.
4.3.1
SLOW OSCILLATOR START-UP
The OST and PLL lock times may not have expired
when the power-up delays have expired.
To avoid this condition, one can enable Two-Speed
Start-up by the device that will run on FRC until the
clock source is stable. Once the clock source is stable,
the device will switch to the selected clock source.
when the power-up delays have expired.
To avoid this condition, one can enable Two-Speed
Start-up by the device that will run on FRC until the
clock source is stable. Once the clock source is stable,
the device will switch to the selected clock source.
4.3.2
WAKE-UP FROM SLEEP ON
INTERRUPT
INTERRUPT
Any source of interrupt that is individually enabled, using
its corresponding control bit in the PIEx registers, can
wake-up the processor from Sleep mode. When the
device wakes from Sleep mode, one of two following
actions may occur:
• If the GIE bit is set, the processor will wake and
its corresponding control bit in the PIEx registers, can
wake-up the processor from Sleep mode. When the
device wakes from Sleep mode, one of two following
actions may occur:
• If the GIE bit is set, the processor will wake and
the Program Counter will begin execution at the
interrupt vector.
interrupt vector.
• If the GIE bit is not set, the processor will wake
and the Program Counter will continue execution
following the SLEEP instruction that initiated Sleep
mode.
following the SLEEP instruction that initiated Sleep
mode.
4.3.3
WAKE-UP FROM SLEEP ON RESET
All sources of device Reset will wake-up the processor
from Sleep mode.
from Sleep mode.
4.3.4
WAKE-UP FROM SLEEP ON
WATCHDOG TIME-OUT
WATCHDOG TIME-OUT
If the Watchdog Timer (WDT) is enabled and expires
while the device is in Sleep mode, the processor will
wake-up. The SWDTEN status bit (RCON2<5>) is set
to indicate that the device resumed operation due to
the WDT expiration. Note that this event does not reset
the device. Operation continues from the instruction fol-
lowing the SLEEP instruction that initiated Sleep mode.
while the device is in Sleep mode, the processor will
wake-up. The SWDTEN status bit (RCON2<5>) is set
to indicate that the device resumed operation due to
the WDT expiration. Note that this event does not reset
the device. Operation continues from the instruction fol-
lowing the SLEEP instruction that initiated Sleep mode.
4.3.5
CONTROL BIT SUMMARY FOR
SLEEP MODES
SLEEP MODES
shows the settings for the bits relevant to
Sleep modes.
TABLE 4-2:
BIT SETTINGS FOR ALL
SLEEP MODES
SLEEP MODES
4.3.6
WAKE-UP DELAYS
The restart delay, associated with waking up from
Sleep and Retention Sleep modes, parallel each other
in terms of clock start-up times. They differ in the time
it takes to switch over from their respective regulators.
The delays for the different oscillator modes are shown
in
Sleep and Retention Sleep modes, parallel each other
in terms of clock start-up times. They differ in the time
it takes to switch over from their respective regulators.
The delays for the different oscillator modes are shown
in
and
, respectively.
Mode
DSEN
DSCONH<7>
Retention Regulator
RETEN
CONFIG7L<0>
SRETEN
RCON4<4>
State
Sleep
x
1
x
Disabled
x
0
0
Disabled
Retention
Sleep
Sleep
x
0
1
Enabled