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Microchip Technology DM183037 Data Sheet

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PIC18F97J94 FAMILY
DS30575A-page 96
 2012 Microchip Technology Inc.
TABLE 5-2:
RCONx BIT OPERATION ON VARIOUS RESETS AND WAKE-UPS  
  
Conditions
PC
DP
S
L
P
EX
T
R
RI
T
O
PD
ID
L
E
CM
BO
R
PO
R
V
DDB
OR
V
DDP
OR
VB
POR
(
)
VB
A
T
(
)
DSPOR:
)
  Loss of V
DDBAT
000000
0
0
0
0
1
0
0
1
1
1
1
1
0
VBAT:
(
  Loss of V
DD
 While V
BAT
 is Established
000000
1
0
0
0
1
0
0
1
1
1
1
u
1
V
DD
 POR:
  Loss of V
DD
000000
0
0
0
0
1
0
0
1
1
1
1
u
u
V
DD
 BOR:
  Brown-out of V
DD
000000
u
u
0
0
1
0
0
u
u
1
u
u
u
POR:
  Loss of V
DDCORE
000000
0
0
0
0
1
0
0
1
1
u
u
u
u
BOR
  Brown-out of V
DDCORE
000000
u
u
0
0
1
0
0
1
u
u
u
u
u
Deep Sleep Exit
000000
1
0
0
0
1
0
0
1
1
u
u
u
u
Retention Deep Sleep Exit
000000
1
0
0
0
1
0
0
0
0
u
u
u
u
MCLR Reset
Operational Mode
000000
u
1
u
u
u
u
u
u
u
u
u
u
u
MCLR Reset in Idle Mode
000000
u
1
u
0
(
)
 
0
(
 
1
(
 
u
u
u
u
u
u
u
MCLR Reset in Sleep Mode
000000
u
1
u
0
(
)
 
0
(
 
0
(
 
u
u
u
u
u
u
u
RESET Instruction Reset
000000
u
u
1
u
u
u
u
u
u
u
u
u
u
Configuration Mismatch Reset
000000
u
u
u
u
u
u
1
u
u
u
u
u
u
WDT Reset
000000
u
u
u
1
u
u
u
u
u
u
u
u
u
WDT Reset in Idle Mode
PC + 2
u
u
u
1
1
(
 
1
(
u
u
u
u
u
u
u
WDT Reset in Sleep Mode
PC + 2
u
u
u
1
0
(
 
0
(
 
u
u
u
u
u
u
u
Interrupt in Idle Mode
with GIE = 0
PC + 2
u
u
u
0
(
)
 
1
(
 
1
(
u
u
u
u
u
u
u
Interrupt in Idle Mode
with GIE = 1
Vector
u
u
u
0
(
)
 
1
(
 
1
(
u
u
u
u
u
u
u
Interrupt in Sleep Mode
With GIE = 0
PC + 2
u
u
u
0
(
)
 
0
(
 
0
(
 
u
u
u
u
u
u
u
Interrupt in Sleep Mode
with GIE = 1
Vector
u
u
u
0
(
)
 
0
(
 
0
(
 
u
u
u
u
u
u
u
CLRWDT Instruction
PC + 2
u
u
u
0
(
)
1
u
u
u
u
u
u
u
u
IDLE Instruction
PC + 2
u
u
u
0
1
1
u
u
u
u
u
u
u
SLEEP Instruction
PC + 2
u
u
u
0
0
0
u
u
u
u
u
u
u
User Instruction Writes ‘1’
PC  +  2
u
1
1
1
0
1
1
1
1
1
1
1
1
User Instruction Writes ‘0’
PC  +  2
0
0
0
0
1
0
0
0
0
0
0
0
0
Note 1:
The SLEEP instruction clears the WDTO bit.
2:
The CLRWDT clears the WDTO bit only when the WDT window feature is disabled or the WDT is in the safe window.
3:
This bit is also set, flagging the loss of state retention even though the true POR condition has not occurred.
4:
This bit is set in hardware only; it can only be cleared in software.
5:
Indicates a V
DD
 POR. Setting the POR bit (RCON<0>) indicates a V
CORE
 POR.
6:
This bit is set when the device is originally powered up, even if power is present on V
BAT
.