Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 171
PIC16(L)F1825/1829
TABLE 18-1:
SRCLK FREQUENCY TABLE
SRCLK
Divider
F
OSC
= 32 MHz
F
OSC
= 20 MHz
F
OSC
= 16 MHz
F
OSC
= 4 MHz
F
OSC
= 1 MHz
111
512
62.5 kHz
39.0 kHz
31.3 kHz
7.81 kHz
1.95 kHz
110
256
125 kHz
78.1 kHz
62.5 kHz
15.6 kHz
3.90 kHz
101
128
250 kHz
156 kHz
125 kHz
31.25 kHz
7.81 kHz
100
64
500 kHz
313 kHz
250 kHz
62.5 kHz
15.6 kHz
011
32
1 MHz
625 kHz
500 kHz
125 kHz
31.3 kHz
010
16
2 MHz
1.25 MHz
1 MHz
250 kHz
62.5 kHz
001
8
4 MHz
2.5 MHz
2 MHz
500 kHz
125 kHz
000
4
8 MHz
5 MHz
4 MHz
1 MHz
250 kHz
REGISTER 18-1:
SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/S-0/0
R/S-0/0
SRLEN
SRCLK<2:0>
SRQEN
SRNQEN
SRPS
SRPR
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
S = Bit is set only
bit 7
SRLEN: SR Latch Enable bit
1 = SR latch is enabled
0 = SR latch is disabled
1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4
SRCLK<2:0>: SR Latch Clock Divider bits
000 = Generates a 1 F
000 = Generates a 1 F
OSC
wide pulse every 4th F
OSC
cycle clock
001 = Generates a 1 F
OSC
wide pulse every 8th F
OSC
cycle clock
010 = Generates a 1 F
OSC
wide pulse every 16th F
OSC
cycle clock
011 = Generates a 1 F
OSC
wide pulse every 32nd F
OSC
cycle clock
100 = Generates a 1 F
OSC
wide pulse every 64th F
OSC
cycle clock
101 = Generates a 1 F
OSC
wide pulse every 128th F
OSC
cycle clock
110 = Generates a 1 F
OSC
wide pulse every 256th F
OSC
cycle clock
111 = Generates a 1 F
OSC
wide pulse every 512th F
OSC
cycle clock
bit 3
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 1:
1 = Q is present on the SRQ pin
0 = External Q output is disabled
0 = External Q output is disabled
If SRLEN = 0:
SR latch is disabled
SR latch is disabled
bit 2
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 1:
1 = Q is present on the SRnQ pin
0 = External Q output is disabled
0 = External Q output is disabled
If SRLEN = 0:
SR latch is disabled
bit 1
SRPS: Pulse Set Input of the SR Latch bit
(1)
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
0 = No effect on set input.
bit 0
SRPR: Pulse Reset Input of the SR Latch bit
(1)
1 = Pulse Reset input for 1 Q-clock period
0 = No effect on Reset input.
0 = No effect on Reset input.
Note 1:
Set only, always reads back ‘0’.