Microchip Technology AC244045 Data Sheet

DS41440C-page 190

 2010-2012 Microchip Technology Inc.

21.6.2

TIMER1 GATE SOURCE 
SELECTION

The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.

21.6.2.1

T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.

21.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.

21.6.2.3

Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
Comparator 1 output (

sync_

C1OUT) can be

synchronized to the Timer1 clock or left asynchronous.
For more information see 

.

21.6.2.4

Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 Gate Control.
The Comparator 2 output (

sync_

C2OUT) can be

synchronized to the Timer1 clock or left asynchronous.
For more information see 

.

21.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See 

 for timing details.

Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.

21.6.4

TIMER1 GATE SINGLE-PULSE 
MODE

When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See

 for timing details.

If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See 

 for

timing details.

21.6.5

TIMER1 GATE VALUE STATUS

When Timer1 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).

21.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).

00

Timer1 Gate Pin

01

Overflow of Timer0
(TMR0 increments from FFh to 00h)

10

Comparator 1 Output 

sync_

C1OUT

(optionally Timer1 synchronized output)

11

Comparator 2 Output 

sync_

C2OUT

(optionally Timer1 synchronized output)

Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.