Microchip Technology AC244045 Data Sheet
PIC16(L)F1825/1829
DS41440C-page 280
2010-2012 Microchip Technology Inc.
25.6.8
ACKNOWLEDGE SEQUENCE
TIMING
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
BRG
) and the SCLx pin is deasserted (pulled high).
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
the Baud Rate Generator counts for T
BRG
. The SCLx pin
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the Baud Rate Generator is
turned off and the MSSPx module then goes into Idle
mode (
automatically cleared, the Baud Rate Generator is
turned off and the MSSPx module then goes into Idle
mode (
25.6.8.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
25.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
BRG
(Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit of the
SSPxSTAT register is set. A T
pin is sampled high while SCLx is high, the P bit of the
SSPxSTAT register is set. A T
BRG
later, the PEN bit is
cleared and the SSPxIF bit is set (
25.6.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 25-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 25-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: T
BRG
= one Baud Rate Generator period.
SDAx
SCLx
SSPxIF set at
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN automatically cleared
Cleared in
T
BRG
T
BRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPxIF
software
SSPxIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCLx
SDAx
SDAx asserted low before rising edge of clock
Write to SSPxCON2,
set PEN
Falling edge of
SCLx = 1 for T
BRG
, followed by SDAx = 1 for T
BRG
9th clock
SCLx brought high after T
BRG
Note: T
BRG
= one Baud Rate Generator period.
T
BRG
T
BRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
T
BRG
to setup Stop condition
ACK
P
T
BRG
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
hardware and the SSPxIF bit is set