Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 297
PIC16(L)F1825/1829
FIGURE 26-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 26-1:
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
APFCON0
RXDTSEL
SDO1SEL
(2)
SS1SEL
(2)
—
T1GSEL
TXCKSEL
—
—
BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INLVLA
(3)
—
—
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INLVLB
(1)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
—
—
—
—
INLVLC
INLVLC7
(1)
INLVLC6
(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INTCON
GIE PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRGL
SPBRG<7:0>
SPBRGH
SPBRG<15:8>
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISB
(1)
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
TRISC
TRISC7
(1)
TRISC6
(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— Unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
* Page provides register information.
Note
1:
PIC16(L)F1829 only.
2:
PIC16(L)F1825 only.
3:
Unshaded cells apply to PIC16(L)F1825 only.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0
bit 1
bit 7/8
bit 0
Note:
This timing diagram shows two consecutive transmissions.
1 T
CY
1 T
CY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)