Microchip Technology AC244045 Data Sheet
PIC16(L)F1825/1829
DS41440C-page 296
2010-2012 Microchip Technology Inc.
26.1.1.5
TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
26.1.1.6
Transmitting 9-bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift nine bits out for each character
transmitted. The TX9D bit of the TXSTA register is the
ninth, and Most Significant, data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See
When the TX9 bit of the TXSTA register is set, the
EUSART will shift nine bits out for each character
transmitted. The TX9D bit of the TXSTA register is the
ninth, and Most Significant, data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See
for more information on the address mode.
26.1.1.7
Asynchronous Transmission Setup:
1.
Initialize the SPBRGH, SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see
the BRGH and BRG16 bits to achieve the desired
baud rate (see
.
2.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
the SYNC bit and setting the SPEN bit.
3.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
4.
Set SCKP bit if inverted transmit is desired.
5.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
control bit. This will cause the TXIF interrupt bit
to be set.
6.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
should be loaded into the TX9D data bit.
8.
Load 8-bit data into the TXREG register. This
will start the transmission.
will start the transmission.
FIGURE 26-3:
ASYNCHRONOUS TRANSMISSION
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
memory, so it is not available to the user.
Word 1
Stop bit
Word 1
Transmit Shift Reg.
Start bit
bit 0
bit 1
bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 T
CY
pin