Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 103
PIC18(L)F2X/4XK22
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.6.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.6.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
6.6.4
PROTECTION AGAINST
SPURIOUS WRITES
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
memory, the write initiate sequence must also be
followed. See
for more detail.
6.7
Flash Program Operation During
Code Protection
Code Protection
See
program memory.
DECFSZ
COUNTER
; loop until holding registers are full
BRA
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF
EECON1, EEPGD
; point to Flash program memory
BCF
EECON1, CFGS
; access Flash program memory
BSF
EECON1, WREN
; enable write to memory
BCF
INTCON, GIE
; disable interrupts
MOVLW
55h
Required
MOVWF
EECON2
; write 55h
Sequence
MOVLW
0AAh
MOVWF
EECON2
; write 0AAh
BSF
EECON1, WR
; start program (CPU stall)
DCFSZ
COUNTER2
; repeat for remaining write blocks
BRA
WRITE_BYTE_TO_HREGS
;
BSF
INTCON, GIE
; re-enable interrupts
BCF
EECON1, WREN
; disable write to memory
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRU
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<21:16>)
—
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
—
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
—
TABLAT
Program Memory Table Latch
—
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2
EEPROM Control Register 2 (not a physical register)
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
Legend:
— = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.