Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 116
2010-2012 Microchip Technology Inc.
9.8
Register Definitions: Interrupt Control
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1
1
= Enables all unmasked interrupts
0
= Disables all interrupts including peripherals
When IPEN = 1:
1
1
= Enables all high priority interrupts
0
= Disables all interrupts including low priority
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
When IPEN = 1:
1
1
= Enables all low priority interrupts
0
= Disables all low priority interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 overflow interrupt
0
= Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1
= Enables the INT0 external interrupt
0
= Disables the INT0 external interrupt
bit 3
RBIE: Port B Interrupt-On-Change (IOCx) Interrupt Enable bit
(2)
1
= Enables the IOCx port change interrupt
0
= Disables the IOCx port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared by software)
0
= TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1
= The INT0 external interrupt occurred (must be cleared by software)
0
= The INT0 external interrupt did not occur
bit 0
RBIF: Port B Interrupt-On-Change (IOCx) Interrupt Flag bit
(1)
1
= At least one of the IOC<3:0> (RB<7:4>) pins changed state (must be cleared by software)
0
= None of the IOC<3:0> (RB<7:4>) pins have changed state
Note
1:
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
mismatch condition and allow the bit to be cleared.
2:
RB port change interrupts also require the individual pin IOCB enables.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.