Microchip Technology MA160014 Data Sheet

DS41412F-page 168

 2010-2012 Microchip Technology Inc.

The Timer1/3/5 register pair (TMRxH:TMRxL)
increments to FFFFh and rolls over to 0000h. When
Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of
the PIR1/2/5 register is set. To enable the interrupt on
rollover, you must set these bits:

• TMRxON bit of the TxCON register

• TMRxIE bits of the PIE1, PIE2 or PIE5 registers

• PEIE/GIEL bit of the INTCON register

• GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in
the Interrupt Service Routine.

For more information on selecting high or low priority
status for the Timer1/3/5 Overflow Interrupt, see

.

 

Timer1/3/5 can only operate during Sleep when set up
in Asynchronous Counter mode. In this mode, an
external crystal or clock source can be used to
increment the counter. To set up the timer to wake the
device:

• TMRxON bit of the TxCON register must be set

• TMRxIE bit of the PIE1/2/5 register must be set

• PEIE/GIEL bit of the INTCON register must be set

• TxSYNC bit of the TxCON register must be set

• TMRxCS bits of the TxCON register must be 

configured

• TxSOSCEN bit of the TxCON register must be 

configured

The device will wake-up on an overflow and execute
the next instruction. If the GIE/GIEH bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.

The secondary oscillator will continue to operate in
Sleep regardless of the TxSYNC bit setting.

The CCP modules use the TMRxH:TMRxL register pair
as the time base when operating in Capture or
Compare mode.

In Capture mode, the value in the TMRxH:TMRxL
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event. 

In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMRxH:TMRxL register pair. This event can be a
Special Event Trigger.

For more information, see 

When any of the CCP’s are configured to trigger a
special event, the trigger will clear the TMRxH:TMRxL
register pair. This special event does not cause a
Timer1/3/5 interrupt. The CCP module may still be
configured to generate a CCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL
register pair becomes the period register for
Timer1/3/5.

Timer1/3/5 should be synchronized and F

OSC

/4 should

be selected as the clock source in order to utilize the
Special Event Trigger. Asynchronous operation of
Timer1/3/5 can cause a Special Event Trigger to be
missed.

In the event that a write to TMRxH or TMRxL coincides
with a Special Event Trigger from the CCP, the write will
take precedence.

For more information, see 

The TMRxH:TMRxL register pair and the
TMRxIF bit should be cleared before
enabling interrupts.