Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 166
2010-2012 Microchip Technology Inc.
FIGURE 12-2:
TIMER1/3/5 16-BIT
READ/WRITE MODE
BLOCK DIAGRAM
READ/WRITE MODE
BLOCK DIAGRAM
12.7
Timer1/3/5 Gate
Timer1/3/5 can be configured to count freely or the
count can be enabled and disabled using Timer1/3/5
Gate circuitry. This is also referred to as Timer1/3/5
Gate Enable.
count can be enabled and disabled using Timer1/3/5
Gate circuitry. This is also referred to as Timer1/3/5
Gate Enable.
Timer1/3/5 Gate can also be driven by multiple
selectable sources.
selectable sources.
12.7.1
TIMER1/3/5 GATE ENABLE
The Timer1/3/5 Gate Enable mode is enabled by
setting the TMRxGE bit of the TxGCON register. The
polarity of the Timer1/3/5 Gate Enable mode is
configured using the TxGPOL bit of the TxGCON
register.
setting the TMRxGE bit of the TxGCON register. The
polarity of the Timer1/3/5 Gate Enable mode is
configured using the TxGPOL bit of the TxGCON
register.
When Timer1/3/5 Gate Enable mode is enabled,
Timer1/3/5 will increment on the rising edge of the
Timer1/3/5 clock source. When Timer1/3/5 Gate
Enable mode is disabled, no incrementing will occur
and Timer1/3/5 will hold the current count. See
Timer1/3/5 will increment on the rising edge of the
Timer1/3/5 clock source. When Timer1/3/5 Gate
Enable mode is disabled, no incrementing will occur
and Timer1/3/5 will hold the current count. See
for timing details.
12.7.2
TIMER1/3/5 GATE SOURCE
SELECTION
SELECTION
The Timer1/3/5 Gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
of four different sources. Source selection is controlled
by the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
The Gate resource, Timer2 Match to PR2, changes
between Timer2, Timer4 and Timer6 depending on
which of the three 16-bit Timers, Timer1, Timer3 or
Timer5, is selected. See
between Timer2, Timer4 and Timer6 depending on
which of the three 16-bit Timers, Timer1, Timer3 or
Timer5, is selected. See
to determine which
Timer2/4/6 Match to PR2/4/6 combination is available
for the 16-bit timer being used.
for the 16-bit timer being used.
12.7.2.1
TxG Pin Gate Operation
The TxG pin is one source for Timer1/3/5 Gate Control.
It can be used to supply an external source to the
Timer1/3/5 Gate circuitry.
It can be used to supply an external source to the
Timer1/3/5 Gate circuitry.
12.7.2.2
Timer2/4/6 Match Gate Operation
The TMR2/4/6 register will increment until it matches
the value in the PR2/4/6 register. On the very next
increment cycle, TMR2/4/6 will be reset to 00h. When
this Reset occurs, a low-to-high pulse will automatically
be generated and internally supplied to the Timer1/3/5
Gate circuitry. See
the value in the PR2/4/6 register. On the very next
increment cycle, TMR2/4/6 will be reset to 00h. When
this Reset occurs, a low-to-high pulse will automatically
be generated and internally supplied to the Timer1/3/5
Gate circuitry. See
for more information.
TABLE 12-3:
TIMER1/3/5 GATE ENABLE
SELECTIONS
SELECTIONS
TxCLK
TxGPOL
TxG
Timer1/3/5
Operation
0
0
Counts
0
1
Holds Count
1
0
Holds Count
1
1
Counts
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
From
Timer1
Circuitry
Block Diagram of Timer1 Example of TIMER1/3/5
TABLE 12-4:
TIMER1/3/5 GATE SOURCES
TxGSS
Timer1/3/5 Gate Source
00
Timer1/3/5 Gate Pin
01
Timer2/4/6 Match to PR2/4/6
(TMR2/4/6 increments to match PR2/4/6)
(TMR2/4/6 increments to match PR2/4/6)
10
Comparator 1 Output sync_C1OUT
(optionally Timer1/3/5 synchronized out-
put)
(optionally Timer1/3/5 synchronized out-
put)
11
Comparator 2 Output sync_C2OUT
(optionally Timer1/3/5 synchronized out-
put)
(optionally Timer1/3/5 synchronized out-
put)
TABLE 12-5:
GATE RESOURCES FOR
TIMER2/4/6 MATCH TO
PR2/4/6
TIMER2/4/6 MATCH TO
PR2/4/6
Timer1/3/5 Resource
Timer1/3/5 Gate Match
Selection
Timer1
TMR2 Match to PR2
Timer3
TMR4 Match to PR4
Timer5
TMR6 Match to PR6