Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 314
2010-2012 Microchip Technology Inc.
18.4
Comparator Interrupt Operation
The comparator interrupt flag will be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see
). The first latch is updated with
the comparator output value, when the CMxCON0
register is read or written. The value is latched on the
third cycle of the system clock, also known as Q3. This
first latch retains the comparator value until another
read or write of the CMxCON0 register occurs or a
Reset takes place. The second latch is updated with
the comparator output value on every first cycle of the
system clock, also known as Q1. When the output
value of the comparator changes, the second latch is
updated and the output values of both latches no
longer match one another, resulting in a mismatch
condition. The latch outputs are fed directly into the
inputs of an exclusive-or gate.
register is read or written. The value is latched on the
third cycle of the system clock, also known as Q3. This
first latch retains the comparator value until another
read or write of the CMxCON0 register occurs or a
Reset takes place. The second latch is updated with
the comparator output value on every first cycle of the
system clock, also known as Q1. When the output
value of the comparator changes, the second latch is
updated and the output values of both latches no
longer match one another, resulting in a mismatch
condition. The latch outputs are fed directly into the
inputs of an exclusive-or gate.
This mismatch condition
is detected by the exclusive-or gate and sent to the
interrupt circuitry. The mismatch condition will persist
until the first latch value is updated by performing a
read of the CMxCON0 register or the comparator
output returns to the previous state.
interrupt circuitry. The mismatch condition will persist
until the first latch value is updated by performing a
read of the CMxCON0 register or the comparator
output returns to the previous state.
When the mismatch condition occurs, the comparator
interrupt flag is set. The interrupt flag is triggered by the
edge of the changing value coming from the exclusive-
or gate. This means that the interrupt flag can be reset
once it is triggered without the additional step of read-
ing or writing the CMxCON0 register to clear the mis-
match latches. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
interrupt flag is set. The interrupt flag is triggered by the
edge of the changing value coming from the exclusive-
or gate. This means that the interrupt flag can be reset
once it is triggered without the additional step of read-
ing or writing the CMxCON0 register to clear the mis-
match latches. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures
and
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE/GIEL and GIE/GIEH bits of
the INTCON register must all be set to enable compar-
ator interrupts. If any of these bits are cleared, the inter-
rupt is not enabled, although the CxIF bit of the PIR2
register will still be set if an interrupt condition occurs.
PIE2 register and the PEIE/GIEL and GIE/GIEH bits of
the INTCON register must all be set to enable compar-
ator interrupts. If any of these bits are cleared, the inter-
rupt is not enabled, although the CxIF bit of the PIR2
register will still be set if an interrupt condition occurs.
18.4.1
PRESETTING THE MISMATCH
LATCHES
LATCHES
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruc-
tion that the CxON bit is set. Since all register writes are
performed as a read-modify-write, the mismatch
latches will be cleared during the instruction read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final write phase.
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruc-
tion that the CxON bit is set. Since all register writes are
performed as a read-modify-write, the mismatch
latches will be cleared during the instruction read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final write phase.
FIGURE 18-3:
COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 18-4:
COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read oper-
ation is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
ation is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1
s for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CxIN+
CxIN
Set CxIF (edge)
CxIF
T
RT
Reset by Software
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
T
RT
Reset by Software
Cleared by CMxCON0 Read