Microchip Technology MA160014 Data Sheet

DS41412F-page 316

 2010-2012 Microchip Technology Inc.

There are four additional comparator features:

• Simultaneous read of comparator outputs

• Internal reference selection

• Hysteresis selection

• Output Synchronization

18.8.1

SIMULTANEOUS COMPARATOR 
OUTPUT READ

The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.

18.8.2

INTERNAL REFERENCE 
SELECTION

There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the Fixed Voltage Reference (FVR) and the
other is the variable Digital-to-Analog Converter (DAC).
The CxRSEL bit of the CM2CON1 register determines
which of these references is routed to the Comparator
Voltage reference output (C

X

V

REF

). Further routing to

the comparator is accomplished by the CxR bit of the
CMxCON0 register. See 

 and 

 for more detail.

18.8.3

COMPARATOR HYSTERESIS

Each Comparator has a selectable hysteresis feature.
The hysteresis can be enabled by setting the CxHYS
bit of the CM2CON1 register. See 

 for more details. 

18.8.4

SYNCHRONIZING COMPARATOR 
OUTPUT TO TIMER1

The Comparator Cx output can be synchronized with
Timer1 by setting the CxSYNC bit of the CM2CON1
register. When enabled, the Cx output is latched on
the falling edge of the Timer1 source clock. To prevent
a race condition when gating Timer1 clock with the
comparator output, Timer1 increments on the rising
edge of its clock source, and the falling edge latches
the comparator output. See the Comparator Block
Diagram (

) and the Timer1 Block Diagram

(

) for more information.

Note 1: Obtaining the status of C1OUT or

C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.

Note 1: The comparator synchronized output

should not be used to gate the external
Timer1 clock when the Timer1
synchronizer is enabled.

2: The Timer1 prescale should be set to 1:1

when synchronizing the comparator
output as unexpected results may occur
with other prescale values.