Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 63

PIC18(L)F2X/4XK22 devices incorporate three
separate on-chip timers that help regulate the Power-
on Reset process. Their main function is to ensure that
the device clock is stable before code is executed.
These timers are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

4.6.1

POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18(L)F2X/4XK22
devices is an 11-bit counter which uses the
LFINTOSC source as the clock input. This yields an
approximate time interval of 2048 x 32

s = 65.6 ms.

While the PWRT is counting, the device is held in
Reset.

The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation.

The PWRT is enabled by clearing the PWRTEN
Configuration bit. 

4.6.2

OSCILLATOR START-UP TIMER 
(OST)

The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or on exit from all
power-managed modes that stop the external oscillator.

4.6.3

PLL LOCK TIME-OUT

With the PLL enabled, the time-out sequence following a
Power-on Reset is slightly different from other oscillator
modes. A separate timer is used to provide a fixed time-
out that is sufficient for the PLL to lock to the main
oscillator frequency. This PLL lock time-out (T

PLL

) is

typically 2 ms and follows the oscillator start-up time-out.

4.6.4

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1.

After the POR pulse has cleared, PWRT time-out
is invoked (if enabled). 

2.

Then, the OST is activated. 

The total time-out will vary based on oscillator
configuration and the status of the PWRT. 

, 

 and 

 all

depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures

 through

 also

apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.

Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (

). This is

useful for testing purposes or to synchronize more than
one PIC

®

 MCU device operating in parallel.

0

0

Unavailable

BOR disabled; must be enabled by reprogramming the Configuration bits.

0

1

Available

BOR enabled by software; operation controlled by SBOREN.

1

0

Unavailable

BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode.

1

1

Unavailable

BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.