Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 64
2010-2012 Microchip Technology Inc.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
, V
DD
RISE < T
PWRT
)
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
DD
): CASE 1
TABLE 4-2:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up
(2)
and Brown-out
Exit from
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms
(1)
+ 1024 T
OSC
+ 2
ms
(2)
1024 T
OSC
+ 2 ms
(2)
1024 T
OSC
+ 2 ms
(2)
HS, XT, LP
66 ms
(1)
+ 1024 T
OSC
1024 T
OSC
1024 T
OSC
EC, ECIO
66 ms
(1)
—
—
RC, RCIO
66 ms
(1)
—
—
INTIO1, INTIO2
66 ms
(1)
—
—
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET