Microchip Technology DV320032 Data Sheet
PIC32MX330/350/370/430/450/470
DS60001185C-page 274
2012-2013 Microchip Technology Inc.
TABLE 30-5:
DC CHARACTERISTICS: OPERATING CURRENT (I
DD
)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
T
A
+85°C for Industrial
-40°C
T
A
+105°C for V-temp
Parameter
No.
Typical
(3)
Maximum
Units
Conditions
Operating Current (I
DD
)
(1,2)
DC20
2.5
4
mA
4 MHz
DC21
6
9
mA
10 MHz (Note 4)
DC22
11
17
mA
20 MHz (Note 4)
DC23
21
32
mA
40 MHz (Note 4)
DC24
30
45
mA
60 MHz (Note 4)
DC25
40
60
mA
80 MHz (Note 4)
DC25a
50
75
mA
100 MHz, -40°C
T
A
+85°C
DC26
100
—
µA
+25ºC, 3.3V
LPRC (31 kHz) (Note 4)
Note 1:
A device’s I
DD
supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2:
The test conditions for I
DD
measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating (ON bit = 0), but the associated PMD bit is clear
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
• MCLR = V
DD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
• RTCC and JTAG are disabled
3:
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
Parameters are for design guidance only and are not tested.
4:
This parameter is characterized, but not tested in manufacturing.