Microchip Technology DV320032 Data Sheet
PIC32MX330/350/370/430/450/470
DS60001185C-page 276
2012-2013 Microchip Technology Inc.
TABLE 30-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (I
PD
)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature
Operating temperature
-40°C
T
A
+85°C for Industrial
-40°C
T
A
+105°C for V-temp
Param.
No.
Typical
(2)
Maximum
Units
Conditions
PIC32MX330/430 Devices Only
Power-Down Current (I
Power-Down Current (I
PD
) (Note 1)
DC40k
12
28
A
-40°C
Base Power-Down Current
DC40l
21
28
A
+25°C
DC40n
128
167
A
+85°C
DC40m
261
419
µA
+105ºC
PIC32MX350/450 Devices Only
Power-Down Current (I
Power-Down Current (I
PD
) (Note 1)
DC40k
12
42
A
-40°C
Base Power-Down Current
DC40l
26
42
A
+25°C
DC40n
220
352
A
+85°C
DC40m
468
749
µA
+105ºC
PIC32MX370/470 Devices Only
Power-Down Current (I
Power-Down Current (I
PD
) (Note 1)
DC40k
33
78
A
-40°C
Base Power-Down Current
DC40l
49
78
A
+25°C
DC40n
281
450
A
+85°C
DC40m
559
895
µA
+105ºC
PIC32MX330/350/370/430/450/470 Devices
Module Differential Current
DC41e
Module Differential Current
DC41e
6.7
—
A
3V
Watchdog Timer Current:
I
WDT
(Note 3)
DC42e
29.1
—
A
3V
RTCC + Timer1 w/32 kHz Crystal:
I
RTCC
(Note 3)
DC43d
1000
—
A
3V
ADC:
I
ADC
(Notes 3,4)
Note 1:
The test conditions for I
PD
measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are dis-
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are dis-
abled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
• MCLR = V
DD
• RTCC and JTAG are disabled
• Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0)
• Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0)
2:
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3:
The
current is the additional current consumed when the module is enabled. This current should be
added to the base I
PD
current.
4:
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.