Freescale Semiconductor Evaluation Board for 56F8037/56F8027 MC56F8037EVM MC56F8037EVM Data Sheet
Product codes
MC56F8037EVM
56F8037/56F8027 Data Sheet, Rev. 8
92
Freescale Semiconductor
when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
read it.
5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
0 = Normal operation (default)
•
1 = All interrupts disabled
5.6.19.5 Reserved—Bits 4-2
This bit field is reserved. Each bit must be set to 1.
5.6.19.6 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1
General
5.7.2
Description of Reset Operation
5.7.2.1 Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in
Figure 5-22 Reset Interface
Table 5-5 Reset Summary
Reset
Priority
Source
Characteristics
Core Reset
RST
Core reset from the SIM
RES
CLK
VAB
PAB
RESET_VECTOR_ADR
READ_ADR