Freescale Semiconductor Evaluation Board for 56F8037/56F8027 MC56F8037EVM User Manuals

Table of Contents

• Part 1 Overview

  6
  • 1.1 56F8037/56F8027 Features

    6
    • 1.1.1 Digital Signal Controller Core

      6
    • 1.1.2 Difference Between Devices

      6
    • 1.1.3 Memory

      6
    • 1.1.4 Peripheral Circuits for 56F8037/56F8027

      7
    • 1.1.5 Energy Information

      8
  • 1.2 56F8037/56F8027 Description

    8
  • 1.3 Award-Winning Development Environment

    9
  • 1.4 Architecture Block Diagram

    9
    • 1.4.1 PWM, TMR and ADC Connections

      9
  • 1.5 Product Documentation

    18
  • 1.6 Data Sheet Conventions

    18
• Part 2 Signal/Connection Descriptions

  19
  • 2.1 Introduction

    19
  • 2.2 56F8037/56F8027 Signal Pins

    24
• Part 3 OCCS

  40
  • 3.1 Overview

    40
  • 3.2 Features

    41
  • 3.3 Operating Modes

    41
  • 3.4 Internal Clock Source

    42
  • 3.5 Crystal Oscillator

    42
  • 3.6 Ceramic Resonator

    43
  • 3.7 External Clock Input - Crystal Oscillator Option

    43
  • 3.8 Alternate External Clock Input

    44
• Part 4 Memory Maps

  44
  • 4.1 Introduction

    44
  • 4.2 Interrupt Vector Table

    45
  • 4.3 Program Map

    47
  • 4.4 Data Map

    48
  • 4.5 EOnCE Memory Map

    50
  • 4.6 Peripheral Memory-Mapped Registers

    51
• Part 5 Interrupt Controller (ITCN)

  68
  • 5.1 Introduction

    68
  • 5.2 Features

    68
  • 5.3 Functional Description

    68
    • 5.3.1 Normal Interrupt Handling

      69
    • 5.3.2 Interrupt Nesting

      69
    • 5.3.3 Fast Interrupt Handling

      69
  • 5.4 Block Diagram

    70
  • 5.5 Operating Modes

    71
  • 5.6 Register Descriptions

    71
    • 5.6.1 Interrupt Priority Register 0 (IPR0)

      73
      • 5.6.1.1 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)-Bits 15-14

        73
      • 5.6.1.2 Low Voltage Detector Interrupt Priority Level (LVI IPL)-Bits 13-12

        73
      • 5.6.1.3 Reserved-Bits 11-10

        73
      • 5.6.1.4 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)- Bits 9-8

        73
      • 5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)- Bits 7-6

        74
      • 5.6.1.6 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)- Bits 5-4

        74
      • 5.6.1.7 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)- Bits 3-2

        74
      • 5.6.1.8 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)- Bits 1-0

        74
    • 5.6.2 Interrupt Priority Register 1 (IPR1)

      75
      • 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)-Bits 15-14

        75
      • 5.6.2.2 MSCAN Wake Up Interrupt Priority Level (MSCAN_WKUP IPL)-Bits 13-12

        75
      • 5.6.2.3 MSCAN Transmit Interrupt Priority Level (MSCAN_TX IPL)-Bits 11-10

        75
      • 5.6.2.4 MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)-Bits 9-8

        75
      • 5.6.2.5 MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)-Bits 7-6

        76
      • 5.6.2.6 FM Command, Data, Address Buffers Empty Interrupt Priority Level (FM_CBE IPL)-Bits 5-4

        76
      • 5.6.2.7 FM Command Complete Interrupt Priority Level (FM_CC IPL)-Bits 3-2

        76
      • 5.6.2.8 FM Error Interrupt Priority Level (FM_ERR IPL)-Bits 1-0

        76
    • 5.6.3 Interrupt Priority Register 2 (IPR2)

      77
      • 5.6.3.1 QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)- Bits 15-14

        77
      • 5.6.3.2 QSPI 1 Transmitter Empty Interrupt Priority Level (QSPI1_XMIT IPL)- Bits 13-12

        77
      • 5.6.3.3 QSPI 1 Receiver Full Interrupt Priority Level (QSPI1_RCV IPL)- Bits 11-10

        77
      • 5.6.3.4 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)- Bits 9-8

        77
      • 5.6.3.5 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)-Bits 7-6

        78
      • 5.6.3.6 GPIOA Interrupt Priority Level (GPIOA IPL)-Bits 5-4

        78
      • 5.6.3.7 GPIOB Interrupt Priority Level (GPIOB IPL)-Bits 3-2

        78
      • 5.6.3.8 GPIOC Interrupt Priority Level (GPIOC IPL)-Bits 1-0

        78
    • 5.6.4 Interrupt Priority Register 3 (IPR3)

      79
      • 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)-Bits 15-14

        79
      • 5.6.4.2 QSCI 1 Receiver Full Interrupt Priority Level (QSCI1_RCV IPL)- Bits 13-12

        79
      • 5.6.4.3 QSCI 1 Receiver Error Interrupt Priority Level (QSCI1_RERR IPL)- Bits 11-10

        79
      • 5.6.4.4 QSCI 1 Transmitter Idle Interrupt Priority Level (QSCI1_TIDL IPL)- Bits 9-8

        79
      • 5.6.4.5 QSCI 1 Transmitter Empty Interrupt Priority Level (QSCI1_XMIT IPL)- Bits 7-6

        80
      • 5.6.4.6 QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)-Bits 5-4

        80
      • 5.6.4.7 QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)- Bits 3-2

        80
      • 5.6.4.8 QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)- Bits 1-0

        80
    • 5.6.5 Interrupt Priority Register 4 (IPR4)

      81
      • 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)- Bits 15-14

        81
      • 5.6.5.2 Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)- Bits 13-12

        81
      • 5.6.5.3 Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)- Bits 11-10

        81
      • 5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)- Bits 9-8

        82
      • 5.6.5.5 I2C Status Interrupt Priority Level (I2C_STAT IPL)-Bits 7-6

        82
      • 5.6.5.6 I2C Transmit Interrupt Priority Level (I2C_TX IPL)-Bits 5-4

        82
      • 5.6.5.7 I2C Receive Interrupt Priority Level (I2C_RX IPL)- Bits 3-2

        82
      • 5.6.5.8 I2C General Call Interrupt Priority Level (I2C_GEN IPL)-Bits 1-0

        82
    • 5.6.6 Interrupt Priority Register 5 (IPR5)

      83
      • 5.6.6.1 Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)- Bits 15-14

        83
      • 5.6.6.2 Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)- Bits 13-12

        83
      • 5.6.6.3 Comparator B Interrupt Priority Level (COMPB IPL)- Bits 11-10

        83
      • 5.6.6.4 Comparator A Interrupt Priority Level (COMPA IPL)- Bits 9-8

        84
      • 5.6.6.5 Timer B, Channel 3 Interrupt Priority Level (TMRB_3 IPL)-Bits 7-6

        84
      • 5.6.6.6 Timer B, Channel 2 Interrupt Priority Level (TMRB_2 IPL)-Bits 5-4

        84
      • 5.6.6.7 Timer B, Channel 1 Interrupt Priority Level (TMRB_1 IPL)-Bits 3-2

        84
      • 5.6.6.8 Timer B, Channel 0 Interrupt Priority Level (TMRB_0 IPL)-Bits 1-0

        84
    • 5.6.7 Interrupt Priority Register 6 (IPR6)

      85
      • 5.6.7.1 Reserved-Bits 15-12

        85
      • 5.6.7.2 PWM Fault Interrupt Priority Level (PWM_F IPL)-Bits 11-10

        85
      • 5.6.7.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)-Bits 9-8

        85
      • 5.6.7.4 ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)-Bits 7-6

        85
      • 5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)-Bits 5-4

        86
      • 5.6.7.6 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)-Bits 3-2

        86
      • 5.6.7.7 Programmable Interval Timer 2 Interrupt Priority Level (PIT2 IPL)-Bits 1-0

        86
    • 5.6.8 Vector Base Address Register (VBA)

      86
      • 5.6.8.1 Reserved-Bits 15-14

        86
      • 5.6.8.2 Vector Address Bus (VAB) Bits 13-0

        87
    • 5.6.9 Fast Interrupt Match 0 Register (FIM0)

      87
      • 5.6.9.1 Reserved-Bits 15-6

        87
      • 5.6.9.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)-Bits 5-0

        87
    • 5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

      87
      • 5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)-Bits 15-0

        87
    • 5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0)

      88
      • 5.6.11.1 Reserved-Bits 15-5

        88
      • 5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)-Bits 4-0

        88
    • 5.6.12 Fast Interrupt 1 Match Register (FIM1)

      88
      • 5.6.12.1 Reserved-Bits 15-6

        88
      • 5.6.12.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)-Bits 5-0

        88
    • 5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

      88
      • 5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)-Bits 15-0

        89
    • 5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)

      89
      • 5.6.14.1 Reserved-Bits 15-5

        89
      • 5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)-Bits 4-0

        89
    • 5.6.15 IRQ Pending Register 0 (IRQP0)

      89
      • 5.6.15.1 IRQ Pending (PENDING)-Bits 16-2

        89
      • 5.6.15.2 Reserved-Bit 0

        89
    • 5.6.16 IRQ Pending Register 1 (IRQP1)

      90
      • 5.6.16.1 IRQ Pending (PENDING)-Bits 32-17

        90
    • 5.6.17 IRQ Pending Register 2 (IRQP2)

      90
      • 5.6.17.1 IRQ Pending (PENDING)-Bits 48-33

        90
    • 5.6.18 IRQ Pending Register 3 (IRQP3)

      90
      • 5.6.18.1 IRQ Pending (PENDING)-Bits 63-49

        90
      • 5.6.18.2 Reserved-Bit 15

        91
    • 5.6.19 Interrupt Control Register (ICTRL)

      91
      • 5.6.19.1 Interrupt (INT)-Bit 15

        91
      • 5.6.19.2 Interrupt Priority Level (IPIC)-Bits 14-13

        91
      • 5.6.19.3 Vector Number - Vector Address Bus (VAB)-Bits 12-6

        91
      • 5.6.19.4 Interrupt Disable (INT_DIS)-Bit 5

        92
      • 5.6.19.5 Reserved-Bits 4-2

        92
      • 5.6.19.6 Reserved-Bits 1-0

        92
  • 5.7 Resets

    92
    • 5.7.1 General

      92
    • 5.7.2 Description of Reset Operation

      92
      • 5.7.2.1 Reset Handshake Timing

        92
    • 5.7.3 ITCN After Reset

      93
• Part 6 System Integration Module (SIM)

  93
  • 6.1 Introduction

    93
  • 6.2 Features

    94
  • 6.3 Register Descriptions

    95
    • 6.3.1 SIM Control Register (SIM_CTRL)

      97
      • 6.3.1.1 Reserved-Bits 15-6

        97
      • 6.3.1.2 OnCE Enable (ONCEEBL)-Bit 5

        97
      • 6.3.1.3 Software Reset (SWRST)-Bit 4

        97
      • 6.3.1.4 Stop Disable (STOP_DISABLE)-Bits 3-2

        97
      • 6.3.1.5 Wait Disable (WAIT_DISABLE)-Bits 1-0

        97
    • 6.3.2 SIM Reset Status Register (SIM_RSTAT)

      98
      • 6.3.2.1 Reserved-Bits 15-7

        98
      • 6.3.2.2 Software Reset (SWR)-Bit 6

        98
      • 6.3.2.3 COP Time-Out Reset (COP_TOR)-Bit 5

        98
      • 6.3.2.4 COP Loss of Reference Reset (COP_LOR)-Bit 4

        98
      • 6.3.2.5 External Reset (EXTR)-Bit 3

        98
      • 6.3.2.6 Power-On Reset (POR)-Bit 2

        98
      • 6.3.2.7 Reserved-Bits 1-0

        99
    • 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3)

      99
      • 6.3.3.1 Software Control Register 0 - 3 (FIELD)-Bits 15-0

        99
    • 6.3.4 Most Significant Half of JTAG ID (SIM_MSHID)

      99
    • 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID)

      99
    • 6.3.6 SIM Power Control Register (SIM_PWR)

      100
      • 6.3.6.1 Reserved-Bits 15-2

        100
      • 6.3.6.2 Large Regulator Standby Mode[1:0] (LRSTDBY)-Bits 1-0

        100
    • 6.3.7 Clock Output Select Register (SIM_CLKOUT)

      100
      • 6.3.7.1 Reserved-Bits 15-10

        101
      • 6.3.7.2 PWM3-Bit 9

        101
      • 6.3.7.3 PWM2-Bit 8

        101
      • 6.3.7.4 PWM1-Bit 7

        101
      • 6.3.7.5 PWM0-Bit 6

        101
      • 6.3.7.6 Clockout Disable (CLKDIS)-Bit 5

        101
      • 6.3.7.7 Clockout Select (CLKOSEL)-Bits 4-0

        101
    • 6.3.8 Peripheral Clock Rate Register (SIM_PCR)

      102
      • 6.3.8.1 Quad Timer B Clock Rate (TMRB_CR)-Bit 15

        102
      • 6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)-Bit 14

        102
      • 6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)-Bit 13

        102
      • 6.3.8.4 Inter-Integrated Circuit Run Clock Rate (I2C_CR)-Bit 12

        102
      • 6.3.8.5 Reserved-Bits 11-0

        102
    • 6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0)

      103
      • 6.3.9.1 Comparator B Clock Enable (CMPB)-Bit 15

        103
      • 6.3.9.2 Comparator A Clock Enable (CMPA)-Bit 14

        103
      • 6.3.9.3 Digital-to-Analog Clock Enable 1 (DAC1)-Bit 13

        103
      • 6.3.9.4 Digital-to-Analog Clock Enable 0 (DAC0)-Bit 12

        103
      • 6.3.9.5 Reserved-Bit 11

        103
      • 6.3.9.6 Analog-to-Digital Converter Clock Enable (ADC)-Bit 10

        103
      • 6.3.9.7 Reserved-Bits 9-7

        104
      • 6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)-Bit 6

        104
      • 6.3.9.9 QSCI 1 Clock Enable (QSCI1)-Bit 5

        104
      • 6.3.9.10 QSCI 0 Clock Enable (QSCI0)-Bit 4

        104
      • 6.3.9.11 QSPI 1 Clock Enable (QSPI1)-Bit 3

        104
      • 6.3.9.12 QSPI 0 Clock Enable (QSPI0)-Bit 2

        104
      • 6.3.9.13 Reserved-Bit 1

        104
      • 6.3.9.14 PWM Clock Enable (PWM)-Bit 0

        104
    • 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1)

      104
      • 6.3.10.1 Reserved-Bit 15

        105
      • 6.3.10.2 Programmable Interval Timer 2 Clock Enable (PIT2)-Bit 14

        105
      • 6.3.10.3 Programmable Interval Timer 1 Clock Enable (PIT1)-Bit 13

        105
      • 6.3.10.4 Programmable Interval Timer 0 Clock Enable (PIT0)-Bit 12

        105
      • 6.3.10.5 Reserved-Bits 11-8

        105
      • 6.3.10.6 Quad Timer B, Channel 3 Clock Enable (TB3)-Bit 7

        105
      • 6.3.10.7 Quad Timer B, Channel 2 Clock Enable (TB2)-Bit 6

        105
      • 6.3.10.8 Quad Timer B, Channel 1 Clock Enable (TB1)-Bit 5

        105
      • 6.3.10.9 Quad Timer B, Channel 0 Clock Enable (TB0)-Bit 4

        105
      • 6.3.10.10 Quad Timer A, Channel 3 Clock Enable (TA3)-Bit 3

        105
      • 6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)-Bit 2

        105
      • 6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)-Bit 1

        106
      • 6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)-Bit 0

        106
    • 6.3.11 Stop Disable Register 0 (SD0)

      106
      • 6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)-Bit 15

        106
      • 6.3.11.2 Comparator A Clock Stop Disable (CMPA_SD)-Bit 14

        106
      • 6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)-Bit 13

        107
      • 6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)-Bit 12

        107
      • 6.3.11.5 Reserved-Bit 11

        107
      • 6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)-Bit 10

        107
      • 6.3.11.7 Reserved-Bits 9-7

        107
      • 6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)-Bit 6

        107
      • 6.3.11.9 QSCI1 Clock Stop Disable (QSCI1_SD)-Bit 5

        107
      • 6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)-Bit 4

        107
      • 6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)-Bit 3

        107
      • 6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)-Bit 2

        107
      • 6.3.11.13 Reserved-Bit 1

        108
      • 6.3.11.14 PWM Clock Stop Disable (PWM_SD)-Bit 0

        108
    • 6.3.12 Stop Disable Register 1 (SD1)

      108
      • 6.3.12.1 Reserved-Bit 15

        108
      • 6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)-Bit 14

        108
      • 6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)-Bit 13

        108
      • 6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)-Bit 12

        108
      • 6.3.12.5 Reserved-Bits 11-8

        108
      • 6.3.12.6 Quad Timer B, Channel 3 Clock Stop Disable (TB3_SD)-Bit 7

        109
      • 6.3.12.7 Quad Timer B, Channel 2 Clock Stop Disable (TB2_SD)-Bit 6

        109
      • 6.3.12.8 Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)-Bit 5

        109
      • 6.3.12.9 Quad Timer B, Channel 0 Clock Stop Disable (TB0_SD)-Bit 4

        109
      • 6.3.12.10 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)-Bit 3

        109
      • 6.3.12.11 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)-Bit 2

        109
      • 6.3.12.12 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)-Bit 1

        109
      • 6.3.12.13 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)-Bit 0

        109
    • 6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)

      109
      • 6.3.13.1 Reserved-Bits 15-2

        110
      • 6.3.13.2 Input/Output Short Address Location (ISAL[23:22])-Bits 1-0

        110
    • 6.3.14 I/O Short Address Location Register Low (SIM_IOSALO)

      110
      • 6.3.14.1 Input/Output Short Address Location (ISAL[21:6])-Bits 15-0

        111
    • 6.3.15 Protection Register (SIM_PROT)

      111
      • 6.3.15.1 Reserved-Bits 15-4

        111
      • 6.3.15.2 Peripheral Clock Enable Protection (PCEP)-Bits 3-2

        111
      • 6.3.15.3 GPIO and Internal Peripheral Select Protection (GIPSP)-Bits 1-0

        112
    • 6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)

      112
      • 6.3.16.1 Reserved-Bits 15-13

        113
      • 6.3.16.2 Configure GPIOA6 (GPS_A6)-Bit 12

        113
      • 6.3.16.3 Configure GPIOA5 (GPS_A5)-Bits 11-10

        113
      • 6.3.16.4 Configure GPIOA4 (GPS_A4)-Bits 9-8

        113
      • 6.3.16.5 Reserved-Bits 7-0

        113
    • 6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)

      113
      • 6.3.17.1 Reserved-Bits 15-14

        114
      • 6.3.17.2 Configure GPIOA14 (GPS_A14)-Bits 13-12

        114
      • 6.3.17.3 Configure GPIOA13 (GPS_A13)-Bits 11-10

        114
      • 6.3.17.4 Configure GPIOA12 (GPS_A12)-Bits 9-8

        114
      • 6.3.17.5 Reserved-Bit 7

        114
      • 6.3.17.6 Configure GPIOA11 (GPS_A11)-Bit 6

        114
      • 6.3.17.7 Reserved-Bit 5

        115
      • 6.3.17.8 Configure GPIOA10 (GPS_A10)-Bit 4

        115
      • 6.3.17.9 Configure GPIOA9 (GPS_A9)-Bits 3-2

        115
      • 6.3.17.10 Configure GPIOA8 (GPS_A8)-Bits 1-0

        115
    • 6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)

      115
      • 6.3.18.1 Reserved-Bit 15

        115
      • 6.3.18.2 Configure GPIOB6 (GPS_B6)-Bits 14-13

        115
      • 6.3.18.3 Configure GPIOB5 (GPS_B5)-Bits 12-11

        116
      • 6.3.18.4 Configure GPIOB4(GPS_B4)-Bits 10-8

        116
      • 6.3.18.5 Configure GPIOB3 (GPS_B3)-Bits 7-6

        116
      • 6.3.18.6 Configure GPIOB2 (GPS_B2)-Bits 5-4

        116
      • 6.3.18.7 Reserved-Bit 3

        116
      • 6.3.18.8 Configure GPIOB1 (GPS_B1)-Bit 2

        116
      • 6.3.18.9 Reserved-Bit 1

        117
      • 6.3.18.10 Configure GPIOB0 (GPS_B0)-Bits 0

        117
    • 6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)

      117
      • 6.3.19.1 Reserved-Bits 15-9

        117
      • 6.3.19.2 Configure GPIOB11 (GPS_B11)-Bit 8

        117
      • 6.3.19.3 Reserved-Bit 7

        117
      • 6.3.19.4 Configure GPIOB10 (GPS_B10)-Bit 6

        117
      • 6.3.19.5 Reserved-Bit 5

        117
      • 6.3.19.6 Configure GPIOB9 (GPS_B9)-Bit 4

        118
      • 6.3.19.7 Reserved-Bit 3

        118
      • 6.3.19.8 Configure GPIOB8 (GPS_B8)-Bit 2

        118
      • 6.3.19.9 Reserved-Bit 1

        118
      • 6.3.19.10 Configure GPIOB7 (GPS_B7)-Bit 0

        118
    • 6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)

      118
      • 6.3.20.1 Reserved-Bits 15-13

        118
      • 6.3.20.2 Configure GPIOD5 (GPS_D5)-Bit 12

        119
      • 6.3.20.3 Reserved-Bits 11-5

        119
      • 6.3.20.4 Configure GPIOC12 (GPS_C12)-Bit 4

        119
      • 6.3.20.5 Reserved-Bit 3

        119
      • 6.3.20.6 Configure GPIOC8 (GPS_C8)-Bit 2

        119
      • 6.3.20.7 Reserved-Bits 1-0

        119
    • 6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width Modulator (SIM_IPS0)

      119
      • 6.3.21.1 Reserved-Bits 15-14

        120
      • 6.3.21.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)-Bit 13

        120
      • 6.3.21.3 Reserved-Bit 12

        120
      • 6.3.21.4 Select Peripheral Input Source for FAULT1 (IPS0_FAULT1)-Bit 11

        120
      • 6.3.21.5 Reserved-Bits 10-9

        121
      • 6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)-Bits 8-6

        121
      • 6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)-Bits 5-3

        121
      • 6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)-Bits 2-0

        121
    • 6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog Converters (SIM_IPS1)

      122
      • 6.3.22.1 Reserved-Bits 15-7

        122
      • 6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1 (IPS1_DSYNC1)-Bits 6-4

        122
      • 6.3.22.3 Reserved-Bit 3

        122
      • 6.3.22.4 Select Peripheral Input Source for SYNC Input to DAC 0 (IPS1_DSYNC0)-Bits 2-0

        123
    • 6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A (SIM_IPS2)

      123
      • 6.3.23.1 Reserved-Bits 15-13

        123
      • 6.3.23.2 Select Peripheral Input Source for TA3 (IPS2_TA3)-Bit 12

        123
      • 6.3.23.3 Reserved-Bits 11-9

        123
      • 6.3.23.4 Select Peripheral Input Source for TA2 (IPS2_TA2)-Bit 8

        123
      • 6.3.23.5 Reserved-Bits 7-5

        124
      • 6.3.23.6 Select Peripheral Input Source for TA1 (IPS2_TA1)-Bit 4

        124
      • 6.3.23.7 Reserved-Bits 3-0

        124
  • 6.4 Clock Generation Overview

    124
  • 6.5 Power-Saving Modes

    124
  • 6.6 Resets

    126
  • 6.7 Clocks

    127
  • 6.8 Interrupts

    129
• Part 7 Security Features

  129
  • 7.1 Operation with Security Enabled

    129
  • 7.2 Flash Access Lock and Unlock Mechanisms

    130
    • 7.2.1 Disabling EOnCE Access

      130
    • 7.2.2 Flash Lockout Recovery Using JTAG

      130
    • 7.2.3 Flash Lockout Recovery using CodeWarrior

      130
    • 7.2.4 Flash Lockout Recovery without mass erase

      130
  • 7.3 Product Analysis

    131
• Part 8 General Purpose Input/Output (GPIO)

  131
  • 8.1 Introduction

    131
  • 8.2 Configuration

    131
  • 8.3 Reset Values

    135
• Part 9 Joint Test Action Group (JTAG)

  140
  • 9.1 56F8037/56F8027 Information

    140
• Part 10 Specifications

  140
  • 10.1 General Characteristics

    140
    • 10.1.1 ElectroStatic Discharge (ESD) Model

      142
  • 10.2 DC Electrical Characteristics

    144
    • 10.2.1 Voltage Regulator Specifications

      146
  • 10.3 AC Electrical Characteristics

    147
  • 10.4 Flash Memory Characteristics

    148
  • 10.5 External Clock Operation Timing

    148
  • 10.6 Phase Locked Loop Timing

    149
  • 10.7 Relaxation Oscillator Timing

    149
  • 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

    151
  • 10.9 Serial Peripheral Interface (SPI) Timing

    152
  • 10.10 Quad Timer Timing

    156
  • 10.11 Queued Serial Communication Interface (QSCI) Timing

    158
  • 10.12 Freescale’s Scalable Controller Area Network (MSCAN) Timing

    159
  • 10.13 Inter-Integrated Circuit Interface (I2C) Timing

    159
  • 10.14 JTAG Timing

    161
  • 10.15 Analog-to-Digital Converter (ADC) Parameters

    162
  • 10.16 Equivalent Circuit for ADC Inputs

    163
  • 10.17 Comparator (CMP) Parameters

    163
  • 10.18 Digital-to-Analog Converter (DAC) Parameters

    164
  • 10.19 Power Consumption

    165
• Part 11 Packaging

  167
  • 11.1 56F8037/56F8027 Package and Pin-Out Information

    167
• Part 12 Design Considerations

  170
  • 12.1 Thermal Design Considerations

    170
  • 12.2 Electrical Design Considerations

    171
• Part 13 Ordering Information

  172
• Part 14 Appendix

  173