Freescale Semiconductor FRDM-FXS-MULTI-B Data Sheet
Document Number: MMA8652FC
Rev. 3.0
06/2014
Rev. 3.0
06/2014
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6.10.5
0x27: PULSE_LTCY Pulse Latency Timer
register
register
Bits LTCY7 – LTCY0 define the time interval that starts after the first
pulse detection. During this time interval, all pulses are ignored.
pulse detection. During this time interval, all pulses are ignored.
NOTE
This timer must be set for
single pulse and for double
pulse.
single pulse and for double
pulse.
Table 81. 0x27 PULSE_LTCY register (Read/Write)
Back to Register Address Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LTCY7
LTCY6
LTCY5
LTCY4
LTCY3
LTCY2
LTCY1
Table 82. PULSE_LTCY register
Bit(s)
Field
Description
7–0
LTCY[7:0]
Latency Time Limit
0000_0000 (default)
0000_0000 (default)