Freescale Semiconductor Demonstration Board for Freescale MC9S08SE8 DEMO9S08EL32AUTO DEMO9S08EL32AUTO Data Sheet
Product codes
DEMO9S08EL32AUTO
Development Support
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
326
Freescale Semiconductor
Figure 17-7. System Background Debug Force Reset Register (SBDFR)
17.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
17.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR
1
1
BDFR is writable only through serial background mode debug commands, not from user programs.
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 17-3. SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.