AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual

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Rev. 3.16 February 2008

Some DDR2 DIMMs exhibit a duty cycle distortion on the first DQS pulse of an incoming read 
request which may cause the processor's DDR interface to miss a beat of data in a read burst.

Undefined system behavior due to incorrect read data.

BIOS should execute the following sequence prior to the DRAM initialization for DDR2-533 and 
DDR2-667:

1. Write 00000800h to F2x[1, 0]9C_xD040F30.

2. Execute the DRAM Initialization sequence as defined in the BIOS and Kernel Developer's Guide 

for AMD Family 10h Processors, order# 31116.

In addition, during DQS position training BIOS should set the DRAM read DQS timing control loop 
range to 32 instead of 64.

No.