AMD Phenom 8450 Triple-Core User Manuals

Table of Contents

• Revision History

  3
• Processor Identification

  5
  • Table 1. CPUID Values for AMD Family 10h Processor Revisions

    5
  • Table 2. Supported Mixed Silicon Revision Configurations

    6
  • Table 3. String Table Reference Per Package Type

    8
  • Table 4. String1 Values for Socket Fr2 (1207) Processors

    9
  • Table 5. String2 Values for Socket Fr2 (1207) Processors

    9
  • Table 6. String1 Values for Socket AM2r2 Processors

    10
  • Table 7. String2 Values for Socket AM2r2 Processors

    10
• F4x164 Fixed Errata Register

  11
• MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)

  12
  • Table 8. OSVW_ID_Length Per Processor Revision

    12
• MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status)

  13
• Product Errata

  14
  • Table 9. Cross-Reference of Product Revision to Errata

    14
  • Table 10. Cross-Reference of Errata to Processor Segments

    16
  • Table 11. Cross-Reference of Errata to Package Type

    17
  • 57 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors

    18
  • 60 Single Machine Check Error May Report Overflow

    19
  • 77 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit

    20
  • 178 Default RdPtrInit Value Does Not Provide Sufficient Timing Margin

    21
  • 244 A DIV Instruction Followed Closely By Other Divide Instructions May Yield Incorrect Results

    22
  • 246 Breakpoint Due to An Instruction That Has an Interrupt Shadow May Be Delivered to the Hypervisor

    23
  • 248 INVLPGA of A Guest Page May Not Invalidate Splintered Pages

    24
  • 254 Internal Resource Livelock Involving Cached TLB Reload

    25
  • 260 REP MOVS Instruction May Corrupt Source Address

    26
  • 261 Processor May Stall Entering Stop-Grant Due to Pending Data Cache Scrub

    27
  • 263 Incompatibility With Some DIMMs Due to DQS Duty Cycle Distortion

    28
  • 264 Incorrect DRAM Data Masks Asserted When DRAM Controller Data Interleaving Is Enabled

    29
  • 269 ITT Specification Exceeded During Power-Up Sequencing

    30
  • 273 Lane Select Function Is Not Available for Link BIST on 8-Bit HyperTransport™ Links In Ganged Mode

    31
  • 274 IDDIO Specification Exceeded During Power-Up Sequencing

    32
  • 278 Incorrect Memory Controller Operation In Ganged Mode

    33
  • 279 HyperTransport™ Link RTT and RON Specification Violations

    34
  • 280 Time Stamp Counter May Yield An Incorrect Value

    35
  • 293 Memory Instability After PWROK Assertion

    36
  • 295 DRAM Phy Configuration Access Failures

    37
  • 297 Single Machine Check Error May Report Overflow

    38
  • 298 L2 Eviction May Occur During Processor Operation To Set Accessed or Dirty Bit

    39
  • 300 Hardware Memory Clear Is Not Supported After Software DRAM Initialization

    40
  • 301 Performance Counters Do Not Accurately Count MFENCE or SFENCE Instructions

    41
  • 302 MWAIT Power Savings May Not Be Realized when Two or More Cores Monitor the Same Address

    42
  • 308 Processor Stall in C1 Low Power State

    43
  • 309 Processor Core May Execute Incorrect Instructions on Concurrent L2 and Northbridge Response

    44
  • 312 CVTSD2SS and CVTPD2PS Instructions May Not Round to Zero

    45
  • 315 FST and FSTP Instructions May Calculate Operand Address in Incorrect Mode

    46
  • 319 Inaccurate Temperature Measurement

    47
• Documentation Support

  48