AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual

41322

Rev. 3.16

February 2008

The DRAM controller 0 (DCT0) and DRAM controller 1 (DCT1) refresh counters may not be 
initialized to the same value using hardware controlled DRAM initialization when operating in 
ganged mode.

Incorrect memory controller operation.

BIOS should apply the following workaround prior to DRAM training when using hardware-
controlled DRAM initialization and F2x110[4] (DctGangEn) is set to 1b.

1. Disable automatic refresh cycles by setting F2x08C[18] (DisAutoRefresh) to 1b.

2. Begin DRAM initialization by setting F2x090[0] to 1b.

3. Poll F2x090[0] until it reads 0b then wait at least 50 microseconds.

4. Enable automatic refresh cycles by clearing F2x08C[18] (DisAutoRefresh) to 0b.

5. Disable automatic refresh cycles by setting F2x08C[18] (DisAutoRefresh) to 1b.

6. Enable automatic refresh cycles by clearing F2x08C[18] (DisAutoRefresh) to 0b.

7. Begin DRAM training.

In addition, when resuming from S3, BIOS should apply the following workaround.

1. Disable automatic refresh cycles by setting F2x08C[18] (DisAutoRefresh) to 1b.

2. Initiate exit from self refresh by setting F2x090[1] to 1b.

3. Poll F2x090[1] until it reads 0b then wait at least 50 microseconds.

4. Enable automatic refresh cycles by clearing F2x08C[18] (DisAutoRefresh) to 0b.

5. Disable automatic refresh cycles by setting F2x08C[18] (DisAutoRefresh) to 1b.

6. Enable automatic refresh cycles by clearing F2x08C[18] (DisAutoRefresh) to 0b.

Yes