AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual

41322

Rev. 3.16 February 2008

After PWROK is asserted, the DRAM DQS DLL may not lock properly.

The system may have degraded memory margins leading to unreliable DRAM signaling. In some 
circumstances, this may cause BIOS to degrade the memory speed.

During DRAM controller (DCT) initialization, system software should perform the following 
workaround to every DCT in the system:

1. Perform a dummy DRAM read to any address on any DIMM attached to the DCT.

2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.

3. Wait at least 300 nanoseconds.

4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C.

5. Wait at least 2 microseconds.

During cold reset or resume from S4 state, the workaround should be performed immediately prior to 
the Receiver Enable Training. During resume from S3 state, the workaround should be applied after 
F2x[1, 0]90[ExitSelfRef] has been cleared and prior to restoring the F2x[1, 0]9C registers.

Yes.