AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual
Product codes
HD8450WCGHBOX
Product Errata
45
Revision Guide for AMD Family 10h Processors
41322
Rev. 3.16
February 2008
312 CVTSD2SS and CVTPD2PS Instructions May Not Round to Zero
Description
The Convert Scalar Double-Precision Floating Point to Scalar Single-Precision Floating Point
(CVTSD2SS) and Convert Packed Double-Precision Floating Point to Packed Single-Precision
Floating Point (CVTPD2PS) instructions do not round to zero when the Flush to Zero and Underflow
Mask bits (MXCSR bits 15 and 11) are set to 1b and the double-precision operand is less than the
smallest single-precision normal number.
(CVTSD2SS) and Convert Packed Double-Precision Floating Point to Packed Single-Precision
Floating Point (CVTPD2PS) instructions do not round to zero when the Flush to Zero and Underflow
Mask bits (MXCSR bits 15 and 11) are set to 1b and the double-precision operand is less than the
smallest single-precision normal number.
Potential Effect on System
The conversion result will yield the smallest single-precision normalized number rather than zero. It
is not expected that this will result in any anomalous software behavior since enabling flush to zero
provides less precise results.
is not expected that this will result in any anomalous software behavior since enabling flush to zero
provides less precise results.
Suggested Workaround
None
Fix Planned
No